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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 6 -channel digital amplifier controller features ? > 100 db dynamic range - system level ? < 0.03% thd+n @ 1 w - system level ? 32 khz to 192 khz sample rates ? internal oscillator circ uit supports 24.576 mhz to 54 mhz crystals ? integrated sample rate converter (src) ? eliminates clock jitter effects ? input sample rate independent operation ? power supply rejection realtime feedback ? spread spectrum modulation - reduces modulation energy ? pwm popguard ? for single-ended mode ? eliminates am frequency interference ? programmable load compensation filters ? support for up to 40 khz audio bandwidth ? digital volume control with soft ramp ? +24 to -127 db in 0.25 db steps ? per channel programmable peak detect and limiter ? spi and i2c host control interfaces ? separate 2.5 v to 5.0 v serial port and host control port supplies dai serial port xtal pwmouta1+ power supply rejection pwmoutb1+ spi/i 2 c host control port scl/cclk sda/cdout ad1/cdin ad0/cs rst int psr_mclk psr_sync psr_data pwm backend control/ status gpio4 gpio5 gpio0 gpio1 gpio2 xto xti pwmouta1- pwmoutb1- pwmouta2+ pwmoutb2+ pwmouta2- pwmoutb2- pwmouta3+ pwmoutb3+ pwmouta3- pwmoutb3- mute dai_mclk dai_sclk dai_lrck dai_sdin1 dai_sdin2 dai_sdin3 volume / limiter multibit ? modulator pwm conversion pwm conversion pwm conversion volume / limiter multibit ? modulator volume / limiter multibit ? modulator pwm clock control auto fs detect sys_clk gpio3 gpio6 psr_en psr_reset ps_sync src may '05 ds633pp1 cs44600
2 ds633pp1 cs44600 general description the cs44600 is a multi-channe l digital-to-pwm class d audio system cont roller including interp olation, sample rate conversion, half- and full-bridge pwm dr iver outputs, and power supply rejecti on feedback in a 64-pin lqfp pack- age.the architecture uses a direct-to-digital approach that ma intains digital signal integrit y to the final output filter, minimizing analog interference effects wh ich negatively affect system performance. the cs44600 integrates on-chip digital volume control, peak detect with limiter, de-emphasis, and 7 gpio?s, allow- ing easy interfacing to many commonly available power st ages. the pwm amplifier can achieve greater than 90% efficiency. this efficiency provides for smaller device package, less heat sink requirements, and smaller power supplies. the cs44600 is ideal for audio systems requiring wide dynam ic range, negligible distortion and low noise, such as a/v receivers, dvd receivers, digital speaker and automotive audio systems. ordering information product description package pb-free temp range container order# cs44600 6 -channel digital amplifier controller lqfp yes -10 to +70c rail cs44600-cqz cs44600 6 -channel digital amplifier controller lqfp yes -10 to +70c tape and reel cs44600-cqzr cs44600 6 -channel digital amplifier controller lqfp yes -40 to +85c rail cs44600-dqz cs44600 6 -channel digital amplifier controller lqfp yes -40 to +85c tape and reel cs44600-dqzr cdb44800 cs44600/800 evaluation board - - - - cdb44800 crd44800 8x50 w half-bridge reference design board - - - - crd44800 CRD44800-ST-FB 8x60 w full-bridge reference design board - - - - CRD44800-ST-FB crd44600-ph-fb 2x100 w full-bridge reference design board - - - - crd44600-ph-fb
ds633pp1 3 cs44600 table of contents 1. characteristics and specifications ........................................................................ 8 specified operating conditions .............. ................ ................ ................ ............. ........... 8 absolute maximum ratings ......... ................ ................ ................ ................ ............. ........... 8 dc electrical characteristics ........................................................................................ 9 digital interface characteristics ................................................................................. 9 pwm output performance characteristics ............................................................. 10 pwm filter characteristics ............................................................................................ 11 switching characteristics - xti ..................................................................................... 11 switching characteristics - sys_clk ............. ................. ................ ................ ............ 12 switching characteristics - pwmouta1-b3 ................................................................ 12 switching characteristics - ps_sync ............. ............................................................. 12 switching characteristics - dai interface ............................................................... 13 switching characteristics - control port - i2c format ...................................... 14 switching characteristics - control port - spi format ..................................... 15 2. pin descriptions .......................................................................................................... .... 16 2.1 i/o pin characteristics ................................................................................................... .. 19 3. typical connection diagrams ................................................................................... 20 4. applications .............................................................................................................. ....... 22 4.1 overview .................................................................................................................. ........ 22 4.2 feature set summary ..................................................................................................... 22 4.3 clock generation .......................................................................................................... ... 23 4.3.1 fsin domain clocking ......................................................................................... 24 4.3.2 fsout domain clocking ...................................................................................... 24 4.4 fsin clock domain mo dules ............................................................................................ 26 4.4.1 digital audio input port ....................................................................................... 26 4.4.2 auto rate detect ................................................................................................. 30 4.4.3 de-emphasis ...................................................................................................... 30 4.5 fsout clock domain module s ......................................................................................... 31 4.5.1 sample rate converter ...................................................................................... 31 4.5.2 load compensation filt er ................................................................................... 31 4.5.3 digital volume and mute control ........................................................................ 31 4.5.4 peak detect / limiter ........................................................................................... 32 4.5.5 pwm engines ..................................................................................................... 32 4.5.6 interpolation filter ............................................................................................... 33 4.5.7 quantizer ............................................................................................................ 33 4.5.8 modulator ............................................................................................................ 33 4.5.9 pwm outputs ...................................................................................................... 33 4.5.10 power supply rejectio n (psr) real-time feedback ....................................... 34 4.6 control port description and timing .......... ...................................................................... 35 4.6.1 spi mode ............................................................................................................ 35 4.6.2 i2c mode ............................................................................................................. 36 4.6.3 gpios ................................................................................................................. 37 4.6.4 host interrupt ...................................................................................................... 37 5. power supply, grounding, and pcb layout ......................................................... 38 5.1 reset and power-up ....................................................................................................... 4 1 5.1.1 pwm popguard? transient control ...... ............................................................. 41 5.1.2 recommended power-up sequence .... ............................................................. 41 5.1.3 recommended psr calib ration sequence .............. ......................................... 42 5.1.4 recommended power-down sequence ............................................................. 43 6. register quick reference .......................................................................................... 44 7. register description .................................................................................................... 48 7.1 memory address pointer (m ap) ...................................................................................... 48
4 ds633pp1 cs44600 7.1.1 increment (incr) ................................................................................................ 48 7.1.2 memory address pointer (mapx) ....... ................................................................ 48 7.2 cs44600 i.d. and revision register (address 01h) (read only) ................................... 48 7.2.1 chip i.d. (chip_idx) ............................................................................................ 48 7.2.2 chip revision (rev_idx) ..................................................................................... 48 7.3 clock configuration and power control (add ress 02h) ................................................... 49 7.3.1 enable sys_clk output (en_sys_clk) ................ ................ ................ ......... 49 7.3.2 sys_clk clock divider se ttings (sys_clk_div[1:0]) ............... ............. ......... 49 7.3.3 pwm master clock divider settings (pwm_mclk_div[1:0]) ............................ 49 7.3.4 power down xtal (pdn_xtal) ........................................................................ 49 7.3.5 power down output mode (pdn_out put_mode) ......................................... 50 7.3.6 power down (pdn) ............................................................................................. 50 7.4 pwm channel power down co ntrol (address 03h) ........................................................ 50 7.4.1 power down pwm channels (pdn_pw mb3:pdn_pwma1) ............................ 50 7.5 misc. configuration (address 04h) ................................................................................... 51 7.5.1 digital interface format (difx) ........................................................................... 51 7.5.2 am frequency hopping (am_freq_hop) ........................................................ 51 7.5.3 freeze controls (freeze) ................................................................................. 51 7.5.4 de-emphasis control (dem[1:0]) ....... ................................................................ 52 7.6 ramp configuration (address 05h) ................................................................................. 52 7.6.1 ramp-up/down setting (ramp[1:0]) ................................................................ 52 7.6.2 ramp speed (ramp_spd[1:0]) ......................................................................... 52 7.7 volume control configuration (address 06h) .................................................................. 53 7.7.1 single volume control (sngvol) ...... ................................................................ 53 7.7.2 soft ramp and zero cross control (szc [1:0]) ................................................... 53 7.7.3 enable 50% duty cycle for mute co ndition (mute_50/50) ............................... 53 7.7.4 soft ramp-down on interface error (srd_err) .............................................. 54 7.7.5 soft ramp-up on recove red interface error (sru_err) ................................. 54 7.7.6 auto-mute (amute) ........................................................................................... 54 7.8 master volume control - in teger (address 07h) .............................................................. 55 7.8.1 master volume control - integer (mstr_ivol[7:0]) .......................................... 55 7.9 master volume control - fr action (address 08h) ............................................................. 55 7.9.1 master volume control - fraction (mstr_fvol[1:0]) ....................................... 55 7.10 channel xx volume contro l - integer (addresses 09h - 0eh) ....................................... 57 7.10.1 channel volume control - integer ( chxx_ivol[7:0]) ...................................... 57 7.11 channel xx volume control1 - fraction (add ress 11h) .............................................. 57 7.12 channel xx volume contro l2 - fraction (address 12h) ................................................ 57 7.12.1 channel volume contro l - fraction (chxx_fvol[1:0]) ................................... 57 7.13 channel mute (address 13h) ................... ...................................................................... 58 7.13.1 independent channel mute (chxx_mute) ..................................................... 58 7.14 channel invert (address 14 h) ........................................................................................ 58 7.14.1 invert signal polarity (chxx_inv) .................................................................... 58 7.15 peak limiter control regi ster (address 15h) ............................................................... 59 7.15.1 peak signal limit all channels (limit_all) .................................................... 59 7.15.2 peak signal limiter enable (limit_en) ........................................................... 59 7.16 limiter attack rate (address 16h) ................................................................................ 59 7.16.1 attack rate (arate[7 :0]) ................................................................................. 59 7.17 limiter release rate (add ress 17h) ........................................................................... 60 7.17.1 release rate (rrate[7 :0]) .............................................................................. 60 7.18 chnl xx load compensation filter - coarse adjust (addresses 18h, 1ah, 1ch, 1eh, 20h, 22h) ............................................................................................................................... ....... 60 7.18.1 channel compensation filter - coar se adjust (chxx_cors[5:0]) ................. 60 7.19 chnl xx load compensation filter - fine adjust (addresses 19h, 1bh, 1dh, 1fh, 21h, 23h) ............................................................................................................................... ....... 61
ds633pp1 5 cs44600 7.19.1 channel compensation filter - fine adjust (chxx_fine[5:0]) ........................ 61 7.20 interrupt mode control (address 28h) ........................................................................... 61 7.20.1 interrupt pin control (int1/int0) ... ................................................................... 61 7.20.2 overflow level/edge select (ovfl_l/e) .......................................................... 62 7.21 interrupt mask (address 29h) ........................................................................................ 62 7.22 interrupt status (address 2ah) (read only) ................................................................. 62 7.22.1 src unlock interrupt (src_unlock) ............................................................ 62 7.22.2 src lock interrupt (src_lock) ..................................................................... 63 7.22.3 ramp-up complete in terrupt (rmpup_done) ............................................... 63 7.22.4 ramp-down complete interrupt (rmpdn_done) .......................................... 63 7.22.5 mute complete interrupt (mut e_done) ........................................................... 63 7.22.6 channel over flow in terrupt (ovfl_int) ........................................................ 63 7.22.7 gpio interrup t condition (gpio_int) .............................................................. 63 7.23 channel over flow status (address 2bh) (read only) ................................................. 64 7.23.1 chxx_ovfl ............... ...................................................................................... 64 7.24 gpio pin in/out (address 2ch) ..................................................................................... 64 7.24.1 gpio in/out selectio n (gpiox_i/o) ................................................................. 64 7.25 gpio pin polarity/type (a ddress 2dh) .......................................................................... 64 7.25.1 gpio polarity/type selection (gpiox _p/t) ..................................................... 64 7.26 gpio pin level/edge trigger (address 2eh) ................................................................. 65 7.26.1 gpio level/edge input sensitive (gpiox_l/e) ............................................... 65 7.27 gpio status register (address 2fh) ....... ...................................................................... 65 7.27.1 gpio pin status (gpiox_status) ................................................................. 65 7.28 gpio interrupt mask regi ster (address 30h) ................................................................ 66 7.28.1 gpio pin interrupt mask (m_gpiox) ............................................................... 66 7.29 pwm configuration register (address 31h) ................................................................. 66 7.29.1 over sample rate selection (osrate) .......................................................... 66 7.29.2 channels a1 and b1 output config uration (a1/b1_out_cnfg) .................... 66 7.29.3 channels a2 and b2 output config uration (a2/b2_out_cnfg) .................... 66 7.29.4 channel a3 output configuration (a3_out_cnfg) ....................................... 67 7.29.5 channel b3 output configuration (b3_out_cnfg) ....................................... 67 7.30 pwm minimum pulse width register (address 32h) .................................................... 67 7.30.1 disable pwmoutxx - signal (di sable_pwmoutxx-) ................................ 67 7.30.2 minimum pwm output pulse settings (min_pulse[4:0]) ............................... 67 7.31 pwmout delay register (address 33h) ...................................................................... 68 7.31.1 differential signal de lay (diff_dly[2:0]) ........................................................ 68 7.31.2 channel delay settin gs (chnl_dly[4:0]) ...................................................... 68 7.32 psr and power supply configuration (add ress 34h) .................................................... 69 7.32.1 power supply rejectio n enable (psr_en) ...................................................... 69 7.32.2 power supply rejection reset (psr _reset) ........... ................ ............. ......... 70 7.32.3 power supply reject ion feedback enable (feedback_en) ......................... 70 7.32.4 power supply sync clock divider settings (ps_sy nc_div[2:0]) ................... 70 7.33 decimator shift/scale (addresses 35h, 36h, 37h) ......................................................... 70 7.33.1 decimator shift (dec_shift[2:0]) ... ................................................................ 70 7.33.2 decimator scale (dec_scale[18:0]) .............................................................. 71 7.34 decimator outd (addresses 3bh, 3ch, 3dh) ................................................................. 71 7.34.1 decimator outd (dec_o utd[23:0]) ................................................................. 71 8. parameter definitions .................................................................................................. 72 9. references ................................................................................................................ ........ 74 10. package dimensions ........................................................................................... 75 11. thermal characteristics ......................................................................................... 76 12. revision history ......................................................................................................... ... 77
6 ds633pp1 cs44600 list of figures figure 1. performance characteri stics evaluation active filter cir cuit......................................... 10 figure 2. xti timings.......................................................................................................... .......... 11 figure 3. sys_clk timings ...... ................ ................ ................ ................ ................ ................ ... 12 figure 4. pwmoutxx timings ..................................................................................................... 12 figure 5. ps_sync timings...................................................................................................... ... 12 figure 6. serial audio interface timing........................................................................................ .13 figure 7. serial audio interface timing - tdm mode.................................................................... 13 figure 8. control port timing - i2c format.......... .......................................................................... 1 4 figure 9. control port timing - spi format......... .......................................................................... 15 figure 10. cs44600 pinout diagram ............................................................................................ 16 figure 11. typical full-bridge co nnection diagram ..................................................................... 20 figure 12. typical half-bridge connection diagr am..................................................................... 21 figure 13. cs44600 data flow diagram (single channel shown) .............................................. 23 figure 14. fundamental mode cryst al configuration ................................................................... 24 figure 15. 3rd overtone crystal configuration ............................................................................. 25 figure 16. cs44600 internal clock generation ............................................................................ 25 figure 17. i2s serial audio formats............................................................................................ .. 27 figure 18. left-justified serial audio formats .............................................................................. 27 figure 19. right-justified serial audio formats............................................................................ 28 figure 20. one line mode #1 serial audio form at....................................................................... 28 figure 21. one line mode #2 serial audio form at....................................................................... 29 figure 22. tdm mode serial audio format .................................................................................. 29 figure 23. de-emphasis curve................................................................................................... .. 30 figure 24. control port timing in spi mode ................................................................................. 35 figure 25. control port timing, i2c slave mode write.................................................................. 36 figure 26. control port timing, i2c slave mode read.................................................................. 36 figure 27. recommended cs44600 power supply decoup ling layout....................................... 38 figure 28. recommended cs44600 crystal circuit layout ......................................................... 39 figure 29. recommended psr circuit layout ............................................................................. 40 figure 30. psr calibration sequence .......................................................................................... 43 figure 31. pwm output delay .................................................................................................... .. 69 figure 32. 64-pin lqfp package drawing ................................................................................... 75
ds633pp1 7 cs44600 list of tables table 1. common dai_mclk frequencies.................................................................................. 24 table 2. dai serial audio port channel allocati ons ..................................................................... 26 table 3. load compensation example settings ........................................................................... 31 table 4. typical pwm switch rate settings....... .......................................................................... 33 table 5. digital audio interface formats.......... ............................................................................. 51 table 6. master integer volume settings...................................................................................... 55 table 7. master fractional volume settings ....... .......................................................................... 56 table 8. channel integer volume settings ................................................................................... 57 table 9. channel fractional volume settings..... .......................................................................... 58 table 10. limiter attack rate settings......................................................................................... .60 table 11. limiter release rate settings............. .......................................................................... 6 0 table 12. channel load co mpensation filter coarse adjust . ...................................................... 61 table 13. channel load co mpensation filter fine adjust............................................................ 61 table 14. pwm minimum pulse width settings............................................................................ 68 table 15. differential signal delay settings........ .......................................................................... 6 8 table 16. channel delay settings............................................................................................... .. 68 table 17. power supply sync clock divider settings................................................................... 70 table 18. decimator shif t/scale coefficient calculation examples .............................................. 71 table 19. revision history ..................................................................................................... ....... 77
8 ds633pp1 cs44600 1. characteristics and specifications (all min/max characteristics and specifications are guaranteed over the specified operating conditions. typical performance characteristics and specifications are derive d from measurements taken at nominal supply voltages and t a = 25 c.) specified operating conditions (gnd = 0 v, all voltages with respect to ground) notes: 1. when using external crystal, vdx = 3.14 v(min). when using clock signal input, vdx = 2.37 v(min). absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 2. any pin except supplies. transient currents of up to 100 ma on the in put pins will not ca use scr latch-up. 3. the maximum over/under voltage is limited by the input current. parameter symbol min typ max units dc power supply digital 2.5 v vd 2.37 2.5 2.63 v xtal (note 1) 2.5 v 3.3 v 5.0 v vdx 2.37 3.14 4.75 2.5 3.3 5.0 2.63 3.47 5.25 v v v pwm interface 3.3 v 5.0 v vdp 3.14 4.75 3.3 5.0 3.47 5.25 v v serial audio interface2.5 v 3.3 v 5.0 v vls 2.37 3.14 4.75 2.5 3.3 5.0 2.63 3.47 5.25 v v v control interface 2.5 v 3.3 v 5.0 v vlc 2.37 3.14 4.75 2.5 3.3 5.0 2.63 3.47 5.25 v v v ambient operating temperature commercial -cqz automotive -dqz t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply digital xtal pwm interface serial audio interface control interface vd vdx vdp vls vlc -0.3 -0.3 -0.3 -0.3 -0.3 3.5 6.0 6.0 6.0 6.0 v v v v v input current (note 2) i in -10ma digital input voltage pwm interface (note 3) serial audio interface control interface v ind-pwm v ind-s v ind-c -0.3 -0.3 -0.3 vdp+0.4 vls+0.4 vlc+0.4 v v v ambient operating temperature -cq (power applied) -dq t a -20 -50 +85 +95 c c storage temperature t stg -65 +150 c
ds633pp1 9 cs44600 dc electrical characteristics (gnd = 0 v, all voltages with respect to ground; dai_ mclk = 12.288 mhz, xtal = 24.576 mhz, pwm switch rate = 384 khz unless otherwise specified.) 4. normal operation is defined as rst = hi with a 997 hz, 0 dbfs input. 5. current consumption increases with increasing xt al clock rates and pwm switch rates. variance be- tween dai clock rates is negligible. 6. i lc measured with no external loading on the sda pin. 7. valid with psrr function enabled and the reco mmended external adc (cs4461) and filtering. 8. power down mode is defined as rst pin = low with all clock and data lines held static. 9. when rst pin = low, the internal oscill ator is active to provide a va lid clock for the sys_clk output. digital interface characteristics (gnd = 0 v, all voltages with respect to ground) 10. serial port signals include: sys_cl k, dai_mclk, dai_sclk, dai_lrck, dai_sdin1-3 control port signals include: scl/cclk, sda/cdout, ad0/cs , ad1/cdin, int, rst , mute pwm signals include: pwmouta1-b3, psr_mcl k, psr_sync, psr_data, ps_sync, gpio[6:0] parameter symbol min typ max units normal operation (note 4) power supply current (note 5) vd = 2.5 v vdx = 3.3 v vdp = 3.3 v vls = 3.3 v vlc = 3.3 v (note 6) i d i dx i dp i ls i lc - - - - - 150 2 1.2 150 250 - - - - - ma ma ma a a power dissipation vd=2.5 v, vdx = vdp = vls = vlc = 3.3 v - 387 500 mw power supply rejection ratio (note 7) (1 khz) (60 hz) psrr - - 15 40 - - db db power-down mode (note 8) power supply current all supplies except vdx (note 9) i pd -80-a parameters (note 10) symbol min typ max units high-level input voltage xtal pwm interface serial audio interface control interface v ih 0.7xvdx 0.7xvdp 0.7xvls 0.7xvlc - - - - - - - - v v v v low-level input voltage xtal pwm interface serial audio interface control interface v il - - - - - - - - 0.2xvdx 0.2xvdp 0.2xvls 0.2xvlc v v v v high-level output voltage at i o = -2 ma pwm interface serial audio interface control interface v oh vdp-1.0 vls-1.0 vlc-1.0 - - - - - - v v v low-level output voltage at i o = 2 ma pwm interface serial audio interface control interface v ol - - - - - - 0.45 0.45 0.45 v v v input leakage current i in --10a input capacitance - - 8 pf
10 ds633pp1 cs44600 pwm output perform ance characteristics (logic ?0? = gnd = 0 v; logic ?1? = vls = vlc; vd = 2.5 v; dai_mclk = 12.288 mhz; xtal= 24.576 mhz; pwm switch rate = 384 khz; fs = 32 khz to 192 khz; measur ement bandwidth is 10 hz to 20 khz unless otherwise specified; performance measurements taken with a full-scale 997 hz.) 11. performance characteristics me asured using filter shown in figure 1 . parameter symbol min typ max unit dynamic performance (note 11) 24-bits a-weighted unweighted 16-bits unweighted 102 99 - 108 105 96 - - - db db db total harmonic distortion + noise (note 11) 24-bits 0 db -20 db -60 db thd+n - - - -90 -77 -45 -85 - - db db db idle channel noise / signal-to-noise ratio - 110 - db interchannel isolation (1 khz) - 100 - db - + - + pwmoutxx+ pwmoutxx- - + - + analog output figure 1. performance characteristi cs evaluation active filter circuit
ds633pp1 11 cs44600 pwm filter characteristics (logic ?0? = gnd = 0 v; logic ?1? = vls = vlc; vd = 2.5 v; dai_mclk = 12.288 mhz; xtal = 24.576 mhz; pwm switch rate = 384 khz; fs = 32 khz to 192 khz; meas urement bandwidth is 10 hz to 20 khz unless otherwise specified.) 12. filter response is not pr oduction tested but is charac terized and guaranteed by design. 13. xtal = 49.152 mhz; pwm switch rate = 768 khz; fs = 96 khz to 192 khz. 14. the equation for the group delay through the sample ra te converter with osrate = 0b is (8.5 / fsi) + (10 / fso) (4.5 / fsi). the equation for the group delay through the sample rate converter with osrate = 1b is (8.5 / fsi) + (20 / fso) (4.5 / fsi). switching charact eristics - xti (vd = 2.5 v, vdp = vlc = vls = 3.3 v, vdx = 2.5 v to 5.0 v; inputs: logic 0 = gnd, logic 1 = vdx) parameter unit min typ max digital filter response (note 12) passband osrate = 0b to -0.01 db corner to -3 db corner osrate = 1b (note 13) to -0.01 db corner to -3 db corner 0 0 0 0 - - - - 1.6 24.0 3.3 44.5 khz khz khz khz frequency response osrate = 0b 10 hz to 20 khz osrate = 1b (note 13) 10 hz to 40 khz -0.8 -1.2 - - +0.02 +0.02 db db group delay (note 14) ms de-emphasis error fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db parameter symbol min typ max unit xti period t clki 18.518 --- 40.69 ns xti high time t clkih 8.34 --- 22.38 ns xti low time t clkil 8.34 --- 22.38 ns xti duty cycle 45 50 55 % external crystal operating frequency 24.576 --- 54 mhz xti t clkih t clkil t clki figure 2. xti timings
12 ds633pp1 cs44600 switching characteristics - sys_clk (vd = 2.5 v, vdp = vlc = vdx = 3.3 v, vls = 2.5 v to 5.0 v, cload = 50 pf) switching characteristics - pwmouta1-b3 (vd = 2.5 v, vls = vlc = vdx = 3.3 v , vdp = 3.3 v to 5.0 v unless otherwise specified, cload = 10 pf) switching characteristics - ps_sync (vd = 2.5 v, vls = vlc = vdx = 3.3 v, vdp = 3.3 v to 5.0 v, cload = 20 pf) parameter symbol min typ max unit sys_clk period t sclki 18.518 --- --- ns sys_clk duty cycle 45 50 55 % parameter symbol min typ max unit pwmoutxx period t pwm 2.60 - 1.18 s rise time of pwmoutxx vdp = 5.0 v vdp = 3.3 v t r - - 1.6 2.1 - - ns ns fall time of pwmoutxx vdp = 5.0 v vdp = 3.3 v t f - - 1.1 1.4 - - ns ns parameter symbol min typ max unit ps_sync period t psclki 592.576 --- --- ns ps_sync duty cycle 45 50 55 % sys_clk t sclki figure 3. sys_clk timings pwmoutxx t pwm t r t f figure 4. pwmoutxx timings ps_sync t psclki figure 5. ps_sync timings
ds633pp1 13 cs44600 switching characteristics - dai interface (vd = 2.5 v, vdx = vdp = vlc = 3.3 v, vls = 2.5 v to 5.0 v; inputs: logic 0 = gnd, logic 1 = vls.) 15. after powering up, the cs44600, rst should be held low un til after the power supp lies and clocks are set- tled. 16. see table 1 on page 26 for suggested mclk frequencies. 17. max dai sample rate is 96 khz for one line and tdm modes of operation. parameters symbol min max units rst pin low pulse width (note 15) 1-ms dai_mclk duty cycle (note 16) 40 60 % dai_sclk duty cycle 45 55 % dai_lrck duty cycle 45 55 % dai sample rate (note 17) f s 32 192 khz dai_sdin setup time before dai_sclk rising edge t ds 10 - ns dai_sdin hold time after dai_sclk rising edge t dh 10 - ns dai_sclk high time t sckh 20 - ns dai_sclk low time t sckl 20 - ns dai_lrck setup time before dai_sclk rising edge t lrcks 25 - ns dai_sclk rising edge before dai_lrck edge t lrckd 25 - ns sckh sckl t t dai_sdinx lrcks t lrckd t dai_sclk dai_lrck ds t dh t figure 6. serial audio interface timing figure 7. serial audio interface timing - tdm mode sckh sckl t t dai_sdin1 dh t ds t lrcks t lrckd t dai_sclk (input) dai_lrck (input) lrcks t msb msb-1
14 ds633pp1 cs44600 switching characteristics - control port - i2c format (vd = 2.5 v, vdx = vdp = vls = 3.3 v; vlc = 2.5 v to 5.0 v; inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) 18. data must be held for sufficient time to bridge the transition time, t f , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 18) t hdd 10 - ns sda setup time to scl rising t sud 250 - ns rise time of scl and sda t r -1000ns fall time scl and sda t f -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 8. control port timing - i2c format
ds633pp1 15 cs44600 switching characteristics - control port - spi format (vd = 2.5 v, vdp = vls = 3.3 v; vlc = 2.5 v to 5.0 v; inputs: logic 0 = gnd, logic 1 = vlc, c l =30pf) 19. data must be held for su fficient time to bridge the transition time of cclk. 20. for f sck <1 mhz. parameter symbol min typ max units cclk clock frequency f sck 0-6.0mhz cs high time between transmissions t csh 1.0 - - s cs falling to cclk edge t css 20 - - ns cclk low time t scl 66 - - ns cclk high time t sch 66 - - ns cdin to cclk rising setup time t dsu 40 - - ns cclk rising to data hold time (note 19) t dh 15 - - ns cclk falling to cdout stable t pd - - 50 ns rise time of cdout t r1 - - 25 ns fall time of cdout t f1 - - 25 ns rise time of cclk and cdin (note 20) t r2 - - 100 ns fall time of cclk and cdin (note 20) t f2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 9. control port timing - spi format
16 ds633pp1 cs44600 2. pin descriptions gnd xti xto vls dai_mclk dai_sclk scl/cclk sda/cdout ad1/cdin ad0/cs int rst vd gnd gpio0 gnd vdp pwmoutb2+ vdp gnd pwmouta1+ pwmouta1- pwmoutb1+ pwmoutb1- pwmouta2+ pwmouta2- psr_mclk psr_sync psr_datal pwmoutb2- pwmouta3+ pwmouta3- pwmoutb3+ pwmoutb3- nc nc nc nc vlc dai_lrck nc dai_sdin1 dai_sdin2 dai_sdin3 gnd vdx gpio3 gpio4 gpio6 gpio2 vd vdp gnd gnd vdp sys_clk gnd psr_reset gpio1 gpio5 mute 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 psr_en ps_sync gnd cs44600 figure 10. cs44600 pinout diagram
ds633pp1 17 cs44600 pin name pin # pin description ps_sync 3 power supply synchronization clock (output ) - the pwm synchronized clock to the switch mode power supply. xti 5 crystal oscillator input ( input ) - crystal oscillator input or accepts an external clock input signal that is used to drive the internal pwm core logic. xto 6 crystal oscillator output (output) - crystal oscillator output. sys_clk 8 external system clock ( output ) - clock output. this pin provides a divided down clock derived from the xti input. dai_mclk 9 digital audio input master clock (input) - master audio clock. dai_sclk 10 digital audio input serial clock (input) - serial clock for the digital audio input inter- face. the clock frequency is a multiple of the left/right clock running at fs. dai_lrck 11 digital audio input left/right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data li ne. the rate is determined by the sampling fre- quency fs. dai_sdin1 dai_sdin2 dai_sdin3 12 13 14 digital audio input serial data ( input ) - input for two?s complement serial audio data. mute 20 mute ( input ) - the device will perform a hard mute on all channels. all internal registers are not reset to their default settings. scl/cclk 21 serial contro l port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interfac e voltage in i2c mode as shown in the typical connection diagram. sda/cdout 22 serial control data ( input/output ) - sda is a data i/o line in i2c mode and requires an external pull-up resistor to the logic interface voltage, as shown in the typical connection diagram.; cdout is the output data line for the control port interface in spi mode. ad1/cdin 23 address bit 1 (i2c)/serial control data (spi) ( input ) - ad1 is a chip address pin in i2c mode.;cdin is the input data line for the control port interface in spi mode. ad0/cs 24 address bit 0 (i2c)/control port chip select (spi) (input ) - ad0 is a chip address pin in i2c mode; cs is the chip select signal in spi mode. int 25 interrupt request (output ) - cmos or open-drain interrupt request output. this pin is driven to the configured active state to indi cate that the pwm controller has status data that should be read by the host. rst 26 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. gpio6 29 general purpose input, output (input/output ) - this pin is configured as an input follow- ing a rst condition. it can be configured as a general purpose input or output which can be individually controlled by the host controller. gpio5 30 general purpose input, output (input/output ) - this pin is configured as an input follow- ing a rst condition. it can be configured as a general purpose input or output which can be individually controlled by the host controller. gpio4 31 general purpose input, output (input/output ) - this pin is configured as an input follow- ing a rst condition. it can be configured as a general purpose input or output which can be individually controlled by the host controller.
18 ds633pp1 cs44600 gpio3 32 general purpose input, output (input/output ) - this pin is configured as an input follow- ing a rst condition. it can be configured as a general purpose input or output which can be individually controlled by the host controller. gpio2 33 general purpose input, output (input/output ) - this pin is configured as an input follow- ing a rst condition. it can be configured as a general purpose input or output which can be individually controlled by the host controller. gpio1 34 general purpose input, output (input/output ) - this pin is configured as an input follow- ing a rst condition. it can be configured as a general purpose input or output which can be individually controlled by the host controller. gpio0 35 general purpose input, output (input/output ) - this pin is configured as an input follow- ing a rst condition. it can be configured as a general purpose input or output which can be individually controlled by the host controller. psr_mclk 49 power supply rejection master clock ( output ) - master audio clock for external psr adc (cs4461). psr_datal 50 power supply rejection input serial data ( input ) - input for serial audio data from external psr adc (cs4461). psr_sync 51 power supply rejection sync clock (input) - synchronization signal for external psr adc (cs4461). psr_reset 52 power supply rejection reset (output ) - the reset pin for the external power supply rejection circuitry. psr_en 2 power supply rejection enable (output ) - the enable pin for the external power supply rejection circuitry. pwmouta1+ pwmouta1- pwmoutb1+ pwmoutb1- pwmouta2+ pwmouta2- pwmoutb2+ pwmoutb2- pwmouta3+ pwmouta3- pwmoutb3+ pwmoutb3- 64 63 61 60 58 57 55 54 47 46 44 43 pwm output ( output ) - pwm control signals for the class d amplifier backend. vdx 7 crystal power ( input ) - positive power supply for the crystal section. vd 19, 27 digital power ( input ) - positive power supply for the digital section. vlc 17 host interface power ( input ) - determines the required signal level for the digital input/output signals for the host interface. vls 16 digital audio interface power ( input ) - determines the required signal level for the digital input signals for the digital audio interface. vdp 39, 45, 56, 62 pwm interface power ( input ) - determines the required signal level for the digital input/output signals for the pwm and gpio interface. gnd 1, 4, 18, 28, 36, 42, 48, 53, 59 digital ground ( input ) - ground reference for digital circuits.
ds633pp1 19 cs44600 2.1 i/o pin characteristics signal name power rail i/o driver receiver rst vlc input - 2.5 v and 3.3/5.0 v ttl compatible. scl/cclk vlc input - 2.5 v and 3.3/5.0 v ttl compatible, with hysteresis. sda/cdout vlc input / output 2.5-5.0 v, cmos/open drain 2.5 v and 3.3/5.0 v ttl compatible, with hysteresis. ad0/cs vlc input - 2.5 v and 3.3/5.0 v ttl compatible, internal pull-up. ad1/cdin vlc input - 2.5 v and 3.3/5.0 v ttl compatible, internal pull-up. int vlc output 2.5-5.0 v, cmos/open drain - mute vlc input - 2.5 v and 3.3/5.0 v ttl compatible. dai_sdinx vls input - 2.5 v and 3.3/5.0 v ttl compatible. dai_sclk vls input - 2.5 v and 3.3/5.0 v ttl compatible. dai_lrck vls input - 2.5 v and 3.3/5.0 v ttl compatible. dai_mclk vls input - 2.5 v and 3.3/5.0 v ttl compatible. sys_clk vls output 2.5-5.0 v, cmos - xti vdx input - 2.5 v and 3.3/5.0 v ttl compatible, internal pull-down. xto vdx output - - gpiox vdp input / output 3.3/5.0 v, cmos/open drain 3.3/5.0 v ttl compatible. pwmoutax+/- vdp output 3.3/5.0 v, cmos - pwmoutbx+/- vdp output 3.3/5.0 v, cmos - psr_mclk vdp output 3.3/5.0 v, cmos - psr_sync vdp input - 3.3/5.0 v ttl compatible, internal pull-up. psr_data vdp input - 3.3/5.0 v ttl compatible, internal pull-up. psr_en vdp output 3.3/5.0 v, cmos - psr_reset vdp output 3.3/5.0 v, cmos - ps_sync vdp output 3.3/5.0 v, cmos -
20 ds633pp1 cs44600 3. typical connection diag rams vd pwmouta1+ pwmouta1- pwmoutb1+ pwmoutb1- vlc 0.1 f +2.5 v to +5.0 v scl/cclk sda/cdout ad1/cdin rst 2 k ? 2 k ? note: resistors are required for i2c control port operation see note dai_sdin1 dai_sdin3 dai_sdin2 dai_lrck dai_sclk ad0/cs int digital audio processor micro- controller gnd dai_mclk pwm in1 out1 control vd pwmouta2+ pwmouta2- pwmoutb2+ pwmoutb2- pwmouta3+ pwmouta3- pwmoutb3+ pwmoutb3- psr_data psr_sync psr_mclk cs4461 adc power supply rail front left surr. left surr. right center subwoofer sys_clk gpio1 gpio3 gpio5 psr_reset psr_en ps_sync power supply sync clock mute status vdx pwm in2 out2 control front right status pwm in3 out3 control status pwm in4 out4 control status pwm in5 out5 control status pwm in6 out6 control status gpio0 gpio6 optional gpio2 gpio4 xtal 24.576 mhz to 54 mhz xti xto vls +2.5 v + 10 f 0.1 f 0.1 f 0.01 f 0.01 f +3.3 v to +5.0 v 0.1 f 0.01 f +2.5 v to +5.0 v 0.1 f 0.01 f +3.3 v to +5.0 v vdp 0.01 f 10 f 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f figure 11. typical full-bridge connection diagram cs44600
ds633pp1 21 cs44600 gnd psr_data psr_sync psr_mclk cs4461 adc power supply rail psr_reset psr_en ps_sync power supply sync clock optional pwmouta1+ pwmouta1- pwmoutb1+ pwmoutb1- pwmouta2+ pwmouta2- pwmoutb2+ pwmoutb2- gpio3 gpio4 front left pwm in1 pwm in2 out1 out2 control status pwm in1 pwm in2 out1 out2 control status pwmouta3+ pwmouta3- pwmoutb3+ pwmoutb3- gpio5 pwm in1 pwm in2 out1 out2 control status front right surr. left surr. right center subwoofer gpio0 gpio1 gpio2 vd vlc 0.1 f +2.5 v to +5.0 v scl/cclk sda/cdout ad1/cdin rst 2 k ? 2 k ? note: resistors are required for i2c control port operation see note dai_sdin1 dai_sdin3 dai_sdin2 dai_lrck dai_sclk ad0/cs int digital audio processor micro- controller dai_mclk vd sys_clk mute vdx xtal 24.576 mhz to 54 mhz xti xto vls +2.5 v + 10 f 0.1 f 0.1 f 0.01 f 0.01 f +3.3 v to +5.0 v 0.1 f 0.01 f +2.5 v to +5.0 v 0.1 f 0.01 f +3.3 v to +5.0 v vdp 0.01 f 10 f 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f figure 12. typical half-bridge connection diagram cs44600
22 ds633pp1 cs44600 4. applications 4.1 overview the cs44600 is a multi-channel digital-to-pwm class d audio system controller including interpolation, sample rate conversion, half- and full-bridge pwm driver outputs, and power supply rejection feedback in a 64-pin lqfp package. the architecture uses a direct-t o-digital approach that maintains digital signal integ- rity to the final output filter, mini mizing analog interference effects wh ich negatively affect system perfor- mance. the cs44600 integrates on-chip sample rate conversion , digital volume control, peak detect with volume limiter, de-emphasis, programmable interrupt conditions, and the ability to change the pwm switch rate to eliminate am frequency interference. the cs44600 also has a programmable load compensation filter, which allows the speaker load to vary while the output filter remains fixed, maintaining a flat frequency re- sponse. for single-ended half-bridge applications pwm popguard ? reduces the transient pops and clicks and realtime power supply feedback reduces noise co upling from the power supply. the pwm amplifier can achieve greater than 90% efficiency. this efficiency pr ovides for a smaller device package, less heat sink requirements, and smaller power supplies. the cs44600 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise such as a/v receivers, dvd receivers, di gital speaker, and automotive audio systems. 4.2 feature set summary core features ? 2.5 v digital core voltage, vd. ? vlc voltage pin for host interface logic levels between 2.5 v and 5.0 v. ? vls voltage pin for digital audio interface logic levels between 2.5 v and 5.0 v. ? vdp voltage pin for pwm backend interfac e logic levels between 3.3 v and 5.0 v. ? vdx voltage pin for clock input signals between 2.5 v and 5.0 v. clocking ? minimum of 128fs dai_mclk for dai serial interface. ? dai interface uses automatic detection of lrck/m clk ratio to configure internal dai/src clocks. ? all pwm processing clocks generated internally via: ? an external crystal - 24.576 mhz to 54 mhz, or ? xti input pin capable of supporting a clock signal at the vdx voltage level. ? programmable divide of xti by 1, 2, 4, 8 for sys_clk output. ? programmable divide of xti by 32, 64, 128, 256 for ps_sync (power supply synchronization signal). digital audio playback ? supports 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz and 192 khz sample frequencies. ? high performance sample rate converter. ? 16, 20 and 24 bit audio sample lengths. ? de-emphasis for 32 khz, 44.1 khz, 48 khz.
ds633pp1 23 cs44600 ? digital volume cont rol with soft ramp. ? individual channel volume gain, at tenuation and mute capability; +24 to -127 db in 0.25 db steps. ? master volume attenuation; +24 to -127 db in 0.25 db steps. ? peak detect and volume limiter with programmable attack and release rates. ? signal-clipping in terrupt indicator. additional features ? contains a two-stage digital output f ilter for speaker impedance compensation. ? provides 7 programmable gpio pins with interrupt generation for easily interfacing to a variety of com- monly available power state parts. interrupts can be masked. ? selectable over-sample rate for increased audio bandwidth. ? power supply clock output, ps_sync, with programmable divider 4.3 clock generation the sources for internal clock generation for the pwm processing are as follows: ? fsin domain: ? dai_mclk, minimum 128fs ? fsout domain: ? xti/xto (fundamental or 3 rd overtone crystal), or ? clock signal on xti (vdx is used to set logic voltage level) dai_sclk dai_sdinx digital audio input port dai_mclk dai_lrck ratio detect sys_clk xti xto pwm engine vol mute peak detect src 2-pole load compensation filter 128fs limiter multibit ? modulator master volume channel volume x2 over sample (osrate) delay delay xtal / clkin 1,2,4,8 clock control pwm_mclk mod_mclk src_mclk (128fs) psr feedback pwm_out+ pwm_out- fsin fsout 1, 1.5, 2, 3, 4, 6, 8 am freq. hop (am_freq_hop) 2.25 1,1.5, 2,4 over sample (osrate) de- emphasis figure 13. cs44600 data flow diagram (single channel shown)
24 ds633pp1 cs44600 4.3.1 fsin domain clocking common dai_mclk frequencies and sample rates are shown in table 1 . 4.3.2 fsout domain clocking to ensure the highest quality conv ersion of pwm signals, the cs4460 0 is capable of operating from a fundamental mode or 3 rd overtone crystal, or a clock signal attached to xti, at a frequency of 24.576 mhz to 54 mhz. if xti is being directly driven by a cloc k signal, xto can be left floating or tied to ground through a pull-down resistor and the internal oscilla tor should be powered down using the pdn_xtal bit in register 02h. mode (sample-rate range) sample rate (khz) dai_mclk (mhz) dai_mclk/lrck ratio ?> 256x 384x 512x 768x 1024x single speed (4 to 50 khz) 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 dai_mclk/lrck ratio ?> 128x 192x 256x 384x 512x double speed (50 to 100 khz) 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 dai_mclk/lrck ratio ?> 64x 96x 128x 192x 256x quad speed (100 to 200 khz) 176.4 n/a n/a 22.5792 33.8688 45.1584 192 n/a n/a 24.5760 36.8640 49.1520 table 1. common dai_mclk frequencies y1 c1 c2 xti xto figure 14. fundamental mode crystal configuration
ds633pp1 25 cs44600 appropriate clock dividers for each functional block and a programmable divider to support an output for switched-mode power supply synchronization are pr ovided. the clock generation for the cs44600 is shown in the figure 16 . y1 l1 c3 c1 c2 xti xto figure 15. 3 rd overtone crystal configuration pwm_mclk src_mclk xto xti mod_mclk sys_clk ps_sync pwm master clock divider system clock divider power supply sync. divider pwm modulator clock divider sample rate converter clock divider figure 16. cs44600 internal clock generation
26 ds633pp1 cs44600 4.4 fsin clock domain modules 4.4.1 digital audio input port the cs44600 interfaces to an external digital audio processor via the digital audio input serial port, the dai serial port. the dai port has 3 stereo data inputs with support for i2s, left-j ustified and right-justified formats. the dai port operates in slave operation only, where dai_lrck, dai_ sclk and dai_mclk are always inputs. the signal dai_lrck must be equal to the sample rate, fs and must be synchronously derived from the supplied master clock, dai_mclk. the serial bit clock, dai_sclk, is used to sample the data bits and must be synchronous ly derived from the master clock. dai_sdin1, dai_sdin2, and dai_sdin 3 are the serial data input pins supplying the associated internal pwm channel modulators. the serial data interface format selection (left-just ified, right-justified, i2s, one line mode, or tdm) for the dai serial port data input pins is configured using the appropriate bits in the register ?misc. configuration (address 04h)? on page 52 . the serial audio data is presented in 2's comple- ment binary form with the msb first in all formats. when operated in one line data mode, 6 channels of pwm data are input on dai_sdin1. in tdm mode, all 6 channels are multiplexed onto the dai_sdin1 data line. table 2 outlines the serial port channel al- locations. the dai digital audio serial ports support 6 formats wit h varying bit depths from 16 to 24 as shown in fig- ure 17 , figure 18 , figure 19 , figure 20 , figure 21 and figure 22 . these formats are selected using the configuration bits in the ?misc. configuration (address 04h)? on page 52 . serial data inputs data mode channel assignments dai_sdin1 normal (i2s,lj,rj) one line #1 or #2 tdm pwmouta1(left channel)/pwmoutb1(right channel) pwmouta1/a2/a3/b1/b2/b3 pwmouta1/a2/a3/b1/b2/b3 dai_sdin2 normal (i2s,lj,rj) one line #1 or #2 tdm pwmouta2(left channel)/pwmoutb2(right channel) not used not used dai_sdin3 normal (i2s,lj,rj) one line #1 or #2 tdm pwmouta3(left channel)/pwmoutb3(right channel) not used not used table 2. dai serial audio port channel allocations
ds633pp1 27 cs44600 4.4.1.1 i2s data format for i2s, data is received most si gnificant bit first, one dai_sclk de lay after the transition of dai_lrck, and is valid on the rising edge of dai_sclk. for the i2s format, the left channel data is presented when dai_lrck is low; the right channel data is presented when dai_lrck is high. 4.4.1.2 left-justif ied data format for left-justified format, dat a is received most significant bit first on the first dai_sclk after a dai_lrck transition and is valid on the rising edge of dai_sc lk. for the left-justified fo rmat, the left channel data is presented when dai_lrck is high and the right channel data is presented when dai_lrck is low. left channel right channel dai_sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb dai_lrck dai_sclk figure 17. i2s serial audio formats i2s mode, data valid on rising edge of dai_sclk bits/sample sclk rates 16 32, 48, 64, 128, 256 fs 18 to 24 48, 64, 128, 256 fs dai_lrck dai_sclk left channel right channel dai_sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 18. left-justified serial audio formats left-justified mode, data valid on rising edge of dai_sclk bits/sample sclk rate(s) 16 32, 48, 64, 128, 256 fs 18 to 24 48, 64, 128, 256 fs
28 ds633pp1 cs44600 4.4.1.3 right-justified data format in the right-justified format, data is received most significant bit first and with the least significant bit pre- sented on the last dai_sclk before the dai_lrck transition and is valid on the rising edge of dai_sclk. for the right-justified fo rmat, the left channel data is presented when dai_lrck is high and the right channel data is presented when dai_lrck is low. either 16 bits per sample or 24 bits per sam- ple are supported. 4.4.1.4 one line mode #1 in one line mode #1 format, data is received most significant bit first on the first dai_sclk after a dai_lrck transition and is valid on the rising edge of dai_sclk. dai_sclk must operate at a 128fs rate. dai_lrck identifies the start of a new frame a nd is equal to the sample period. dai_lrck is sam- pled as valid on the same clock edge as the most sign ificant bit of the first data sample and must be held high for 64 dai_sclk periods. each time slot is 20 bits wide, with the valid data sample left-justified within the time slot. valid data lengths are 16, 18, or 20 bits. valid samples rates for this mode are 32 khz to 96 khz. left channel right channel 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 dai_sdinx dai_lrck dai_sclk figure 19. right-justified serial audio formats right-justified mode, data valid on rising edge of dai_sclk bits/sample sclk rate(s) 16 32, 48, 64, 128, 256 fs 24 48, 64, 128, 256 fs pwmoutb3 dai_lrck dai_sclk lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb 20 clks 20 clks 20 clks 20 clks 20 clks dai_sdin1 pwmouta1 pwmoutb1 pwmouta2 pwmoutb2 pwmouta3 left channels right channels figure 20. one line mode #1 serial audio format
ds633pp1 29 cs44600 4.4.1.5 one line mode #2 in one line mode #2 format, data is received most significant bit first on the first dai_sclk after a dai_lrck transition and is valid on the rising edg e of dai_sclk. dai_sclk must operate at a 256 fs rate. dai_lrck identifies the start of a new frame and is equal to the sample period. dai_lrck is sam- pled as valid on the same clock edge as the most significant bit of the first data sample and must be held high for 128 dai_sclk periods. each time slot is 24 bits wide, with the valid data sample left-justified with- in the time slot. valid data lengths are 16, 18, 20, or 24 bits. valid samples rates for this mode are 32 khz to 96 khz. 4.4.1.6 tdm mode in tdm mode format, data is received most signific ant bit first on the first dai_sclk after a dai_lrck transition and is valid on the rising edge of da i_sclk. dai_sclk must operate at a 256 fs rate. dai_lrck identifies the start of a new frame and is equal to the sample peri od. dai_lrck is sampled as valid on the proceeding clock edge as the most si gnificant bit of the first dat a sample and must be held valid for at least 1 dai_sclk period. each time slot is 32 bits wide, with the valid data sample left-justified within the time slot. valid data lengths are 16, 18, 20, 24 or 32 bits. valid sample s rates for this mode are 32 khz to 96 khz. pwmoutb3 dai_lrck dai_sclk lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb msb dai_sdin1 pwmouta1 pwmoutb1 pwmouta2 pwmoutb2 pwmouta3 128 clks 128 clks 24 clks 24 clks 24 clks 24 clks 24 clks 24 clks left channels right channels figure 21. one line mode #2 serial audio format pwmoutb2 dai_lrck dai_sclk lsb msb lsb msb lsb msb lsb msb lsb msb dai_sdin1 pwmouta1 pwmouta2 pwmoutb1 pwmouta3 256 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks lsb msb pwmoutb3 32 clks 32 clks figure 22. tdm mode serial audio format
30 ds633pp1 cs44600 4.4.2 auto rate detect the cs44600 will automatically determine the incomi ng sample rate, dai_lrck, to master clock, dai_mclk, ratio and configure the appropriate internal clock divider such that the sample rate convertor receives the required clock rate. a minimum dai_mclk rate of 128fs is required for proper operation. the supported dai_mclk to dai_lrck ratios are shown in table 1 on page 26 . 4.4.3 de-emphasis the cs44600 includes on-chip digital de-emphasis filt ers. the de-emphasis feature is included to accom- modate older audio recordings that utilize pre-em phasis equalization as a me ans of noise reduction. figure 23 shows the de-emphasis curve. the frequency response of the de-emphasis curve will scale pro- portionally with changes in samp le rate, fs. the required de-emphasis filter for 32 khz, 44.1 khz, or 48 khz is selected via the de -emphasis control bits in ?misc. configuration (address 04h)? on page 52 . gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 23. de-emphasis curve
ds633pp1 31 cs44600 4.5 fsout clock domain modules 4.5.1 sample rate converter one of the characteristics of a pwm amplifier is that the frequency content of out-of-band noise generated by the modulator is dependent on the pwm switchi ng frequency. the power stage external lc and snub- ber filter component values are ba sed on this switching frequency. to accommodate input sample rates ranging from 32 khz to 192 khz the cs44600 utilizes a sample rate converter (src) and several clock- ing modes that keep the pw m switching frequency fixed. the src supports a range of sample rate conversion to upsample rates from 32 khz to 192 khz to a fixed fsout sample rate. this is typically 384 khz for mo st audio applications. the src also allows the pwm modulator output to be independent of the input clock jitter since the output of the src is clocked from a very stable crystal or o scillator. this results in very low ji tter pwm output and higher dynamic range. 4.5.2 load compensation filter to accommodate varying speaker impedances, the cs44600 incorporates a 2-pole load compensation filter to adjust the effective frequency response of the on-card l/c de-modulation filter. the frequency re- sponse of the 2-pole inductor/capacitor filter used on the board to filter out the high-frequency pwm switching clock is highly dependant on th e resistive load (speaker) attached. if the l/c filter implemented was designed for a low impedance load (4 ? speaker), but an 8 ? speaker was attached, the frequency response would have a la rge peaking near the resonant frequency of the l/c. the peaking usually starts at around 15 khz, with about a +4 db of gain at around 20 khz. this phe- nomenon will cause the system to not meet the frequency re sponse requirements as specified by dolby labs. by using the programmable 2-pole load compensation filter, the overall frequency response of the system can be modified to cut the amount of peaking. the 2 pol es of the filter are inde pendently configurable and are concatenated to form the overall filter response. the first filter is defined as a coarse setting. this filter should be programmed to provide most of the attenuation of the peaking. the second filter, defined as the fine adjust, is used to achiev e incremental improvements to the overall frequency response. table 3 shows example register settings based on an ou tput filter that ha s been designed for a 4 ? load imped- ance. see ?channel compensation filter - coarse adjust (chxx_cors[5:0])? on page 62 and ?channel compensation filter - fine adju st (chxx_fine[5:0])? on page 63 . 4.5.3 digital volume and mute control the cs44600 provides two levels of volume control. a master volume control re gister is used to set the volume level across all pwm channels . the register value, which select s a volume range of +24 db to - 127 db in 0.25 db steps, is used to control the overa ll volume setting of all th e amplifier channels. volume control changes are programmable to ramp in increments of 0.125 db at a variable rate controlled by the szc[1:0] bits in ?volume control configuration (address 06h)? on page 55 . each pwm channel?s output level is controlled via a channel volume control register operating over the range of +24 db to -127 db attenuation with 0.25 db resolution. see ?channel xx volume control - inte- load impedance coarse filter setting fine filter setting 6 ? -1.2 db 0 db 8 ? -1.8 db 0 db 16 ? -3.4 db 0 db table 3. load compensation example settings
32 ds633pp1 cs44600 ger (addresses 09h - 10h)? on page 58 . volume control changes are programmable to ramp in increments of 0.125 db at a variable rate controlled by the szc[1:0] bits. each pwm channel output can be independently mu ted via mute control bits in the register ?channel mute (address 13h)? on page 60 . when enabled, each chxx_mute bit attenuates th e corresponding pwm channel to its maximum value (-127 db). when the chxx_mute bit is disabled, t he corresponding pwm channel returns to the atten- uation level set in the volume control register. the attenuation is ramped up and down at the rate spec- ified by the szc[1:0] bits. 4.5.4 peak detect / limiter the cs44600 has the ability to limit the maximu m signal amplitude to prevent clip ping. the ?peak limiter control register (address 15h)? on page 60 is used to configure the peak detect and limiter engines? op- eration. peak signal limiting is performed by digital attenuation. the attack rate is determined by the ?lim- iter attack rate (address 16h)? on page 61 . the release rate is determined by the ?limiter release rate (address 17h)? on page 61 . 4.5.5 pwm engines there are three stereo pwm engines: pwm_eng_ 1, pwm_eng_2, and pwm_ eng_3. each pwm can handle one stereo pair and connects to a driver or a pair of drivers, depending on the output configuration. each pwm engine receives the master clock, pwm_ mclk, from the clock control block, and the asso- ciated channel data and audio sample timings from the sample rate converter. the ?pwm configuration register (address 31h)? on page 68 is used to configure the pwm engines? op- eration. this register controls the parameters of the pwm engines and can only be changed while the pwm engines are in the power down state. features: ? up to 6 channel support ? 64 quantization levels ? psrr compensation feedback ? programmable over sampling - interpolate times 2 (2 x) or filter by-pass. by-pass is intended for 384 khz (single-speed) pwm switch rate support. the interpolate 2x filter is used to upsample the data to support a pwm switch rate of 768 khz (double speed mode). this enables the output frequency re- sponse to extend past 20 khz when the dai sample rate is 96 khz or 192 khz. ? programmable registers to move pwm edges for dela y adjustment. this lowe rs the overall noise con- tribution by allowing each pwm edge to switch at different times. ? programmable modulation setup ? min/max pwm pulse width allowed ? programmable modulation index. the table below shows the ava ilable settings for the pwm engine for a 384 khz/768 khz or 421.875 khz/843.75 khz pwm fswitch rate verses th e supported fsin sample rates using the src with a maximum pwm_mclk of 49.152 mhz/54 mhz.
ds633pp1 33 cs44600 4.5.6 interpolation filter the times 2 (2x) interpolation filter is part of the quantizer and is used to up sample the data to support a higher pwm switch rate. the interpolator is controlled by the osrate bit in the ?pwm configuration register (address 31h)? on page 68 and employs digital filtering to provide high quality interpolation. 4.5.7 quantizer the quantizer takes the input audio data at a typica l 384 khz or 768 khz rate (depending on whether the 2x interpolator is on or not) from the interpolator as input. when psr r is enabled, the quantizer takes the input from psrr decimator and uses it to correct for power_supply noise. it also provides protection through min/max pulse limiting hard ware to generate outputs that wo uldn?t violate minimum pulse widths required at the pwm drivers. its stereo outputs are running at the pwm switch rate. 4.5.8 modulator each output from the quantizer goes to the modulator. the modulator takes the parallel input data at a 384 khz or 768 khz, depending on the setting of the os rate bit, and changes the parallel data to serial, one-bit outputs. the result is modulated pulses at the selected switch rate with 64 level resolution. the modulator maintains low frequency audio signals, allowi ng the output to reproduce all low frequency audio content down to 0 hz. 4.5.9 pwm outputs the modulators outputs are followed by the pwm conf iguration block. these signals are routed through delay control blocks where they generate two outputs each. these final outputs are modulated pulses run- ning at the pwm switch rate as determined by the settings shown in table 4 . circuitry in the pwm configuration block guarantees, that no pulses shorter than the minimum pulse are generated. the minimum pulse width is configur ed using the min_pulse[4:0] bits in the ?pwm minimum pulse width register (address 32h)? on page 69 . the pwm configuration block also provides the pwm output signal delay mechanism. adjusting the out- puts? delays allows for managing the switching noise between channel s, as well as differential signal noise. the ?pwmout delay register (address 33h)? on page 70 specify the delay amount for each pwm output. the delay is measured in periods of pwm_mclk. table 4. typical pwm sw itch rate settings fsin (khz) fsout ( khz ) using src quant level osrate pwm switch rate (khz) required xtal or sys_clk (mhz) 64 1 384 24.576 64 2 768 49.152 64 1 421.875 27.000 64 2 843.75 54.000 32, 44.1, 48, 88.2, 96, 176.4, 192 384 32, 44.1, 48, 88.2, 96, 176.4, 192 421.875
34 ds633pp1 cs44600 4.5.10 power supply rejecti on (psr) real-time feedback inherent to most class d power amp lifier solutions is the requirement for a clean and well-regulated high voltage power supply. any noise or tones present on the power rail will couple throug h each channel?s power mosfet output device. these spurious distortion components on the output signal consist of dis- crete tones, which can be audible from the speaker, and tones that modulate around the audio signal be- ing played. to remove the requirement for a well-regulated power supply, and therefore reduce overall system costs, the rejection of harmonic distortion from the power supply and tones coupled onto the power rail is ac- complished by the patented power supply rejection r ealtime feedback. by using the cs4461 and associ- ated attenuation circuitry, the scaled ac and dc co mponents of the power supply rail are fed back into the pwm modulator. all delays through the feedback path have been minimized such that the noise can- cellation is accomplished in real-tim e allowing for substantia l noise rejection within the output audio signal. see ?typical connection diagrams? on page 22 for examples on how to connect the external adc (cs4461) to the cs44600 for psr feedback, ?recommended psr calibration sequence? on page 44 , and the cs4461 datasheet.
ds633pp1 35 cs44600 4.6 control port description and timing the control port is used to access the registers, allowing the cs44600 to be configured for the desired op- erational modes and formats. the operation of the cont rol port may be complete ly asynchronous with re- spect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i2c, with the cs 44600 acting as a slave device. spi mode is selected if there is a high to lo w transition on the ad0/cs pin, after the rst pin has been brought high. i2c mode is selected by connec ting the ad0/cs pin through a resistor to vlc or gnd, thereby permanently selecting the desired ad0 bit address state. 4.6.1 spi mode in spi mode, cs is the cs44600 chip select signal, cclk is the control port bit clock (input into the cs44600 from the microcontroller), cdin is the inpu t data line from the micr ocontroller, cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 24 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and mu st be 1001111. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the r egister that is to be updated. the ne xt eight bits are the data which will be placed into the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired there is a map auto increm ent capability, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for succes sive read or writes. if incr is set to a 1, the map will autoincrement after each byte is written, allowing block writes of successive registers. autoincrement reads are not sup- ported. to read a register, the map has to be set to the correct address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the m ap auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance figure 24. control port timing in spi mode
36 ds633pp1 cs44600 4.6.2 i2c mode in i2c mode, sda is a bidirectional da ta line. data is clocke d into and out of the pa rt by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least significant bits of the chip address and should be connected through a resistor to vlc or gnd as de sired. the state of the pins is sensed while the cs44600 is being reset. the signal timings for a read and write cycle are shown in figure 25 and figure 26 . a start condition is defined as a falling transition of sda while the clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs44600 after a start condition consists of a 7 bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address field are fixed at 10011. to communicate with a cs44600, the chip address field, which is the first byte sent to the cs44600, should match 10011 followed by the settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address poin ter (map) which selects the register to be read or written. if the op- eration is a read, the contents of the register pointed to by the map will be output. setting the auto incre- ment bit in map allows successive writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs44600 after each input byte is read, and is input to the cs44600 from the microcontroller after each transm itted byte. autoincrement reads are not supported. since the read operation can not set the map, an aborted write operation is used as a preamble. as shown in figure 26, the write operation is aborted after the acknowledge for the map byte by sending a stop condition. t he following pseudocode illustrate s an aborted write operatio n followed by a read oper- ation. send start condition. send 10011xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10011xx1(chip address & read operation). 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 25. control port timing, i2c slave mode write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 26. control port timing, i2c slave mode read
ds633pp1 37 cs44600 receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. each byte is separated by an acknowledge bit. 4.6.3 gpios the cs44600 gpio pins will ha ve the following features: ? data direction control. ? programmable open-drain or push-pull driver when configured as an output pin. ? maskable interrupt for gpio[3:0] pins when set as a general purpose input. ? level-sensitive or edge-trigger ev ent selector for all gpio pins. 4.6.4 host interrupt the cs44600 has a comprehensive interr upt capability. the int output pi n is intended to drive the inter- rupt input pin on the host microcontroller. the int pi n may be set to be active low, active high or active low with an open-drain driver. this last mode is used for active low, wired-or hook-ups, with multiple pe- ripherals connected to the microcontroller interrupt input pin. many conditions can cause an interrupt, as listed in th e interrupt status register descriptions. see ?inter- rupt status (address 2ah) (read only)? on page 64. each source may be masked off through mask register bits. in addition, each source may be set to rising edge, falling edge, or level sensitive. combined with the option of level sensitive or edge sensitive modes wit hin the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.
38 ds633pp1 cs44600 5. power supply, grounding, and pcb layout the cs44600 requires a 2.5 v digital power supply for the core logic. in order to support a number of pwm backend solutions, separate vdp power pins are provided to condition the interface sign als to support up to 5.0 v levels. the vdp power pins control the voltage leve ls for all pwm interface signals, psr interface signals and gpio for control and status. extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capac- itors are recommended. it is necessary to decouple the po wer supply by placing capac itors directly between the power and ground of the cs44600. the recommended procedur e is to place the lowest value capacitor as close as physically possible to each power pin. decoupling capacitors should be as near to the pins of the cs44600 as pos- sible, with the low value ceramic capacitor being the near est and mounted on the same side of the board as the cs44600 to minimize inductance effects. figure 27 shows the recommended power supply decoupling layo ut. u1 is the cs44600. c2, c3, c6, c8, c10, c12, c14, and c16 are 0.01 f x7r capacitors. these should be placed as close as possible to their respective power supply pins. c1, c4, c5, c7, c9, c11, c13, c15, and c1 7 are 0.1 f x7r capacitors. c18 is a 10 f electrolytic capacitor. top and bottom ground fill should be used as much as possib le around all components shown. figure 27. recommended cs44600 power supply decoupling layout
ds633pp1 39 cs44600 figure 28 shows the recommended crystal circuit layout. u1 is the cs44600. c1 and c2 are the vdx power supply decoupling capacitors. y1 is the crystal and c3, c4, l1 and c5 are the associated components for the crystal circuit. l1 and c5 are only used for 3 rd overtone crystals. c3 and c4 should have a c0g (npo) dielectric. care should be taken to minimize the dist ance between the cs44600 xti/xto pins an d c3. top and bottom ground fill should be used as much as possible around and in between a ll crystal circuit components to minimize noise. figure 28. recommended cs44600 crystal circuit layout
40 ds633pp1 cs44600 figure 29 shows the recommended psr circuit layout. see the cs4461 datasheet for further details on the input buffer and other associated external components. u1 is the cs4461 and u2 is the input buffer op-amp. all supply decoupling should be placed as close as possible to th eir respective power supply pins. c4 should have a c0g (npo) dielectric and be placed as close as possible to the cs4461 ain+/- pins. the cs4461 and input buffer should be placed on the board between the cs44600 and the high voltage power supply. the sens e point of the high volt- age power supply (the point at which the input buffer taps off of the high voltage power supply) should be close to the middle of the amplifier output channels. if the sense poin t is taken at either end of the amplifier output channels, inaccurate reading could occur due to localized channel di sturbances causing noise on the high voltage power sup- ply. optimally, the high voltage power c onnector should also be placed in the middle of the amplifier output channels figure 29. recommended psr circuit layout
ds633pp1 41 cs44600 5.1 reset and power-up reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and configuration pins are stable. it is also recommended that the rst pin be activated if the voltage supplies drop below the recommended operating condition to prevent power-glitch- related issues. when rst is low, the cs44600 enters a low-power mode and all internal states are reset, including the control port and registers. when rst is high, the control port becomes operational and the desired settings should be loaded into the control re gisters. writing a 0 to the pdn bit in the power control register will then cause the part to leave the low- power state and begin operation. 5.1.1 pwm popguard ? transient control the cs44600 uses popguard ? technology to minimize the effects of output transients during power-up and power-down. this technique reduces the audio transients commonly produced by half-bridge, single- supply amplifiers when implemented with external dc-blocking capacito rs connected in series with the audio outputs. each pwm channel can individually be controlled for ramp-up and ramp-down cycles. when the device is initially powered-up and config ured for ramp-up, the pwmoutxx outputs are clamped to gnd. following a write of a 0 to the pdn_pwmxx bit in the pwm channel power down control (ad- dress 03h) register, each output begins to increase the pwm duty cycle to ward the bias voltage point. by a speed set by the ramp_spdx bits, the pwmoutxx outputs will ramp from 0 v (gnd) and reach the bias point (50% pwm duty cycle). th is gradual voltage ramp ing allows time for the external dc-blocking capacitor to charge to the bias voltage, minimizing the power-up transient. to prevent an audible transient at the next power-on , the dc-blocking capacitors must fully discharge be- fore turning off the power. if full discharge does not occur, a transient will occur wh en the audio outputs are initially clamped to gnd. to prevent transients at power-down, the user must first mute the outputs. when this occurs, audio output ceases and the pwm duty cycle is approximately 50% duty cycle, which represents the mute condition. once the channels are powered down, the pwmoutxx outputs slowly decrease the dc offset until it reaches gnd. the time required to reach gnd is det ermined by the ramp_spdx bits. this allows the dc-blocking capacitors to slowly disc harge. once this charge is dissi pated, the power to the device may be turned off, and the system is ready for the next power-on. 5.1.2 recommended power-up sequence 1. hold rst low until the power supply and clocks are stable. in this state, all control port registers are reset to the default settings. th e pwmoutxx pins are driven low. 2. the sys_clk pin will output a divided-down clock of the signal attached to the xti pin. if the mute pin is held low, sys_cl k is equal to the xti frequency. if the mute pin is held high, then sys_clk is equal to the xti frequency divided by 2. 3. bring rst high. the device will remain in a low power state and all regi sters will contai n the specified default value. the lo gic state of the mute pin will be latched and used to specify the clock divider for sys_clk. the control port will be accessible at this time. 4. with the cs44600 in the power-down state, pdn bi t is ?1?b, set up the re quired pwm configuration registers and volume control registers. configure th e gpio pins for normal operation. do not enable the power stages at this time. 5. mute all channel outputs by setting th e corresponding chxx_mute bits to ?1?b.
42 ds633pp1 cs44600 6. when driving a single-ended (half-bridged) power ou tput stage, set the ramp[1:0] bits to ?11?b and the required ramp speed, to initiate a ramp cycle when the channel is powered on. set min_pulse[4:0] to ?00000?b. 7. set the pdn bit to ?0?b to take th e cs44600 out of the power-down state. 8. start all clocks on the dai interf ace (dai_mclk, dai_sclk, dai_lrck ). this will initiate the src to begin the lock sequence. the src lock function can be configured to cause an interrupt condition when lock has been completed. this will be indi cated by an active int signal. 9. wait for the src to lock. 10. if using the psr feedback, jump to ?recommended psr calibration sequence? on page 44 . when finished, continue to step 12. if not using psr feedback, continue to step 12. 11. set the appropriate gpio pin, or other c ontrol signal, to enable the power output stage. 12. enable each channel?s pwm modulator by setting th e pdn_pwmxx bit to ?0?b. if full-bridged, go to step 14. if single-ended (hal f-bridged), this will init iate a sequence which will slowly increase the dc voltage, from 0v to vpower2, ac ross the ac coupling capacitor. this will eliminate th e instantaneous charge across the capacitor which would have caused an audible pop from the speaker. 13. wait for the ramp-up sequence to complete. the ra mp-up function can be configured to cause an interrupt condition when the ramp period has comp leted. this will be indicated by an active int signal. once the ramp-up sequence has completed, set the ramp[1:0] bits to ?01?b 14. for full-bridged power output stage configuratio ns, the ramp-up sequence is not required. enabling the power outp ut stage will not cause an aud ible pop from the speaker. 15. if using the psr feedback, set the feedback_en bit to ?1?b. 16. un-mute all active channels. 17. at this point, the cs44600 is ready to accept audio samples and begin playback. 5.1.3 recommended psr ca libration sequence 1. set the dec_shift[2:0]/dec _scale[18:0] coefficient (c psr ) to decimal 1.0 (register 35h = 22h, 36h = 00h, 37h = 00h). 2. set the psr_reset bit to ?1?b. 3. set the psr_en bit to ?1?b. 4. set the psr_en bit to ?0?b. 5. read dec_outd[23:0]. 6. see figure 30 to adjust the dec_shift[2: 0]/dec_scale[18:0] registers. 7. continue recommended power-up sequence.
ds633pp1 43 cs44600 5.1.4 recommended power-down sequence 1. mute all channel outputs by setting th e corresponding chxx_mute bits to ?1?b. 2. when driving a single-ended (half-bridged) power output stage, set the ramp[1:0] bits to ?01?b and the required ramp speed, to initiate a ramp cycle when the channel is powered down. 3. power down each channel?s pwm modulator by sett ing the pdn_pwmxx bit to ?1?b. if single-ended, this will initiate a sequence which will slowly decrease the dc voltage, from vpower2 to 0 v, across the ac-coupling capacitor. 4. the ramp-down function can be configured to cause an interrupt condition when the ramp period has completed. this will be indicated by an active int signal. 5. once the ramp-down sequence has completed, set th e appropriate gpio pin, or other control signal, to power down the power output stage. 6. for full-bridged power output stage configurations , the ramp-down sequence is not required. powering down the power output stage will not cause an audib le pop from the speaker. 7. concurrently with the ramp-down sequence, if de sired, stop all clocks on the dai interface (dai_mclk, dai_sclk, dai_lrck). 8. set the pdn bit to ?1?b to put the cs44600 in the power down state. set psr_en = 1b set psr_en = 0b read dec_outd[23:0] 3fef90h < dec_outd[23:0] < 400fffh? done dec_outd[23:0] > 400fffh? yn c psr =c psr - 9bh set psr_reset = 1b c psr =c psr + 9bh yn figure 30. psr calibration sequence
44 ds633pp1 cs44600 6. register quick reference addr function 7 6 5 4 3 2 1 0 01h id / rev. chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0 page 48 default 1 1 0 0 0 0 0 1 02h clock config / power control en_sys_clk sys_clk_div1 sys_clk_div0 pwm_mclk_div1 pwm_mclk_div0 pdn_xtal pdn_output_mo de pdn page 49. default 1 0 0 0 0 0 0 1 03h chnl power down reserved reserved pdn_pwmb3 pdn_pwma3 pdn_pwmb2 pdn_pwma2 pdn_pwmb1 pdn_pwma1 page 50. default 1 1 1 1 1 1 1 1 04h misc. config. dif2 dif1 dif0 reserved am_freq_hop freeze dem1 dem0 page 51 default 0 0 1 0 0 0 0 0 05h ramp config reserved reserved reserved ramp1 ramp0 reserved ramp_spd1 ramp_spd0 page 52 default 0 0 0 0 0 0 0 1 06h vol control config sngvol szc1 szc0 reserved mute_50/50 srd_err sru_err amute page 53 default 0 1 0 0 0 0 0 1 07h master vol. control - integer mstr_ivol7 mstr_ivol6 mstr_ivol5 mstr_ivol4 mstr_ivol3 mstr_ivol2 mstr_ivol1 mstr_ivol0 page 55 default 0 0 0 0 0 0 0 0 08h master vol. control - fraction reserved reserved reserved reserved reserved reserved mstr_fvol1 mstr_fvol0 page 55 default 0 0 0 0 0 0 0 0 09h channel a1 vol. control - integer cha1_ivol7 cha1_ivol6 cha1_ivol5 cha1_ivol4 cha 1_ivol3 cha1_ivol2 cha1_ivol1 cha1_ivol0 page 57 default 0 0 0 0 0 0 0 0 0ah channel b1 vol. control - integer chb1_ivol7 chb1_ivol6 chb1_ivol5 chb1_ivol4 chb 1_ivol3 chb1_ivol2 chb1_ivol1 chb1_ivol0 page 57 default 0 0 0 0 0 0 0 0 0bh channel a2 vol. control - integer cha2_ivol7 cha2_ivol6 cha2_ivol5 cha2_ivol4 cha 2_ivol3 cha2_ivol2 cha2_ivol1 cha2_ivol0 page 57 default 0 0 0 0 0 0 0 0 0ch channel b2 vol. control - integer chb2_ivol7 chb2_ivol6 chb2_ivol5 chb2_ivol4 chb 2_ivol3 chb2_ivol2 chb2_ivol1 chb2_ivol0 page 57 default 0 0 0 0 0 0 0 0 0dh channel a3 vol. control - integer cha3_ivol7 cha3_ivol6 cha3_ivol5 cha3_ivol4 cha 3_ivol3 cha3_ivol2 cha3_ivol1 cha3_ivol0 page 57 default 0 0 0 0 0 0 0 0 0eh channel b3 vol. control - integer chb3_ivol7 chb3_ivol6 chb3_ivol5 chb3_ivol4 chb 3_ivol3 chb3_ivol2 chb3_ivol1 chb3_ivol0 page 57 default 0 0 0 0 0 0 0 0 0fh reserved reserved reserved reserved reserved reserved reserved reserved reserved default 00 000000 10h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 00 000000
ds633pp1 45 cs44600 11h channel vol. con- trol 1-fraction chb2_fvol1 chb2_fvol0 cha2_fvol1 cha2_fvol0 chb1_fvol1 chb1_fvol0 cha1_fvol1 cha1_fvol0 page 57. default 0 0 0 0 0 0 0 0 12h channel vol. con- trol 2-fraction reserved reserved reserved reserved chb3_fvol1 chb3_fvol0 cha3_fvol1 cha3_fvol0 page 57 default 0 0 0 0 0 0 0 0 13h channel mute reserved reserved chb3_mute cha3_mute chb2_mute cha2_mute chb1_mute cha1_mute page 58 default 0 0 0 0 0 0 0 0 14h channel invert reserved reserved chb3_inv cha3_inv chb2_inv cha2_inv chb1_inv cha1_inv page 58 default 0 0 0 0 0 0 0 0 15h peak limiter control reserved reserved reserved reserved reserved reserved limit_all limit_en page 59 default 0 0 0 0 0 0 0 0 16h limiter attack rate arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0 page 59 default 0 0 0 1 0 0 0 0 17h limiter release rate rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 page 60 default 0 0 1 0 0 0 0 0 18h chnl a1 comp. filter - coarse adj reserved reserved cha1_cors5 cha1_cors4 cha1_ cors3 cha1_cors2 cha 1_cors1 cha1_cors0 page 60 default 0 0 0 0 0 0 0 0 19h chnl a1 comp. filter - fine adj reserved reserved cha1_fine5 cha1_fine4 cha1_fine3 cha1_fine2 cha1_fine1 cha1_fine0 page 61 default 0 0 0 0 0 0 0 0 1ah chnl b1 comp. filter - coarse adj reserved reserved chb1_cors5 chb1_cors4 chb1_ cors3 chb1_cors2 chb 1_cors1 chb1_cors0 page 60 default 0 0 0 0 0 0 0 0 1bh chnl b1 comp. filter - fine adj reserved reserved chb1_fine5 chb1_fine4 chb1_fine3 chb1_fine2 chb1_fine1 chb1_fine0 page 61 default 0 0 0 0 0 0 0 0 1ch chnl a2 comp. filter - coarse adj reserved reserved cha2_cors5 cha2_cors4 cha2_ cors3 cha2_cors2 cha 2_cors1 cha2_cors0 page 60 default 0 0 0 0 0 0 0 0 1dh chnl a2 comp. filter - fine adj reserved reserved cha2_fine5 cha2_fine4 cha2_fine3 cha2_fine2 cha2_fine1 cha2_fine0 page 61 default 0 0 0 0 0 0 0 0 1eh chnl b2 comp. filter - coarse adj reserved reserved chb2_cors5 chb2_cors4 chb2_ cors3 chb2_cors2 chb 2_cors1 chb2_cors0 page 60 default 0 0 0 0 0 0 0 0 1fh chnl b2 comp. filter - fine adj reserved reserved chb2_fine5 chb2_fine4 chb2_fine3 chb2_fine2 chb2_fine1 chb2_fine0 page 61 default 0 0 0 0 0 0 0 0 20h chnl a3 comp. filter - coarse adj reserved reserved cha3_cors5 cha3_cors4 cha3_ cors3 cha3_cors2 cha 3_cors1 cha3_cors0 page 60 default 0 0 0 0 0 0 0 0 addr function 7 6 5 4 3 2 1 0
46 ds633pp1 cs44600 21h chnl a3 comp. filter - fine adj reserved reserved cha3_fine5 cha3_fine4 cha3_fine3 cha3_fine2 cha3_fine1 cha3_fine0 page 61 default 0 0 0 0 0 0 0 0 22h chnl b3 comp. filter - coarse adj reserved reserved chb3_cors5 chb3_cors4 chb3_cors3 chb3_cors2 chb3_cors1 chb3_cors0 page 60 default 0 0 0 0 0 0 0 0 23h chnl b3 comp. filter - fine adj reserved reserved chb3_fine5 chb3_fine4 chb3_fine3 chb3_fine2 chb3_fine1 chb3_fine0 page 61 default 0 0 0 0 0 0 0 0 24h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 25h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 26h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 27h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 28h interrupt mode control int1 int0 reserved reserved reserved reserved reserved ovfl_l/e page 61 default 0 0 0 0 0 0 0 0 29h interrupt mask m_src_unlock m_src_lock m_rmpup_done m_rmpdn_done m_mute_done m_ovfl_int reserved reserved page 62 default 0 0 0 0 0 0 0 0 2ah interrupt status src_unlock src_lock rmpup_do ne rmpdn_done mute_done ovfl_int gpio_int reserved page 62 default 0 0 0 0 0 0 0 0 2bh chnl over flow sta- tus reserved reserved chb3_ovfl cha3_ovfl chb2_ovfl cha2_ovfl chb1_ovfl cha1_ovfl page 64 default 0 0 0 0 0 0 0 0 2ch gpio pin i/o reserved gpio6_i/o gpio5_i/o gpio4_i/o gpio3_i/o gpio2_i/o gpio1_i/o gpio0_i/o page 64 default 0 0 0 0 0 0 0 0 2dh gpio pin polar- ity/type reserved gpio6_p/t gpio5_p/t gpio4_p/t gpio3_p/t gpio2_p/t gpio1_p/t gpio0_p/t ppage 64 default 0 1 1 1 1 1 1 1 2eh gpio pin level/edge trigger reserved gpio6_l/e gpio5_l/e gpio4_l/e gpio3_l/e gpio2_l/e gpio1_l/e gpio0_l/e page 65 default 0 0 0 0 0 0 0 0 2fh gpio pin status reserved gpio6_status gpio5_status gpio4_status gpio3_status gpio2_status gpio1_status gpio0_status page 65 default x x x x x x x x 30h gpio interrupt mask reserved reserved reserved reserved m_gpio3 m_gpio2 m_gpio1 m_gpio0 page 66 default 0 0 0 0 0 0 0 0 31h pwm config osrate reserved reserved a1/b1_o ut_cnfg a2/b2_out_cnfg a3_out_cnfg b3_out_cnfg reserved page 66 default 0 0 0 0 0 0 0 0 addr function 7 6 5 4 3 2 1 0
ds633pp1 47 cs44600 32h pwm minimum pulse width disable_ pwmoutxx- reserved reserved min_pulse4 min_pulse3 min_pulse2 min_pulse1 min_pulse0 page 67 default 0 0 0 0 0 0 0 0 33h pwmout delay diff_dly2 diff_dly1 diff_dly0 chnl_dly4 chnl_dly3 chnl_dly2 chnl_dly1 chnl_dly0 page 68 default 0 0 0 0 0 0 0 0 34h psr / power supply config psr_en psr_reset feedback_ en reserved reserved ps_sync_div2 ps_sync_div1 ps_sync_div0 page 69 default 0 0 0 0 0 0 0 0 35h psr_decimator scaled reserved dec_shift2 dec_shift1 dec_shift0 rese rved dec_scaled18 dec_scaled17 dec_scaled16 page 70 default 0 0 1 0 0 0 1 0 36h psr_decimator scaled dec_scaled15 dec_scaled14 dec_scaled13 dec_scaled12 dec_scaled11 dec_scaled10 dec_scaled09 dec_scaled08 page 70 default 0 1 0 1 1 0 0 0 37h psr_decimator scaled dec_scaled07 dec_scaled06 dec_scaled05 dec_scaled04 dec_scaled03 dec_scaled02 dec_scaled01 dec_scaled00 page 70 default 0 1 1 0 1 0 0 0 38h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 39h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 3ah reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 3bh psr_decimator outd dec_outd23 dec_outd22 dec_outd21 dec_outd20 dec_outd19 dec_outd18 dec_outd17 dec_outd16 page 71 default 0 0 0 0 0 0 0 0 3ch psr_decimator outd dec_outd15 dec_outd14 dec_outd13 dec_outd12 dec_outd11 dec_outd10 dec_outd09 dec_outd08 page 71 default 0 0 0 0 0 0 0 0 3dh psr_decimator outd dec_outd07 dec_outd06 dec_outd05 dec_outd04 dec_outd03 dec_outd02 dec_outd01 dec_outd00 page 71 default 0 0 0 0 0 0 0 0 addr function 7 6 5 4 3 2 1 0
48 ds633pp1 cs44600 7. register description all registers are read/write except for i.d. and revision register, interrupt status an d decimator outd registers which are read only. see the following bit definition tables for bit assignment informatio n. the default state of each bit after a power-up sequence or reset is listed in each bit description. 7.1 memory address pointer (map) not a register 7.1.1 increment (incr) default = 1 function: memory address pointer auto increment control ? 0 - map is not incremented automatically. ? 1 - internal map is automatically in cremented after each read or write. 7.1.2 memory addr ess pointer (mapx) default = 0000001 function: memory address pointer (map) . sets the register address that will be read or written by the control port. 7.2 cs44600 i.d. and revision re gister (address 01h) (read only) 7.2.1 chip i.d. (chip_idx) default = 1101 function: i.d. code for the cs44600. permanently set to 1101. 7.2.2 chip revision (rev_idx) default = 0001 function: cs44600 revision level. revision a is coded as 0001. 76543210 incr map6 map5 map4 map3 map2 map1 map0 76543210 chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0
ds633pp1 49 cs44600 7.3 clock configuration and power control (address 02h) 7.3.1 enable sys_clk output (en_sys_clk) default = 1 function: this bit enables the driv er for the sys_clk si gnal. if the sys_clk output is unused, this bit should be set to ?0?b to disable the driver. 7.3.2 sys_clk clock divider settings (sys_clk_div[1:0]) default = 00 function: these two bits determine the divi der for the xtal clock signal for generating the sys_clk signal. during a reset condition, with the rst input pin held low, the logic level on the mute input pin will determine the divider used for the sys_clk output. if mute is pulled low, the sys_clk divider will be set to divide the clock frequency on xti by a factor of 1. if the mute pin is pulled high, t he sys_clk output will be set to perform a divide-by-2 on the xti clock. the state of the mute pin will be latched on the rising edge of the rst . the mute pin can then be used as defined. 7.3.3 pwm master clock divider settings (pwm_mclk_div[1:0]) default = 00 function: these two bits determine the divider for the xtal cl ock signal for generating the pwm_mclk signal. 7.3.4 power down xtal (pdn_xtal) default = 0 0 - crystal oscillator circuit is running. 1 - crystal oscillator cir cuit is powered down. function: this bit is used to power down th e crystal oscillator circ uitry when not being used. when using a clock signal attached to the xti input, this bit should be set to ?1?b. 76 5 4 3 2 10 en_sys_clk sys_clk_div1 sys_clk_div0 pwm_mclk_d iv1 pwm_mclk_div0 pdn_xtal pdn_output_mode pdn sys_clk_div[1:0] sys_cl k clock divider 00 use state of mute input pin following rst condition 01 divide by 2 10 divide by 4 11 divide by 8 pwm_mclk_div[1:0] pwm master clock divider 00 divide by 1 01 divide by 2 10 divide by 4 11 divide by 8
50 ds633pp1 cs44600 7.3.5 power down output mode (pdn_output_mode) default = 0 0 - pwm outputs are driven low during power down 1 - pwm outputs are driven to the inactive state during power down function: this bit is used to select the powe r-down state of the pwm output sign als. when set to 0, each channel which has been powered down, follo wing the ramp-down cycle if enable d, will drive the output signals, pwmoutxx+ and pwmoutxx-, low. when set to 1, each channel which has been powe red down, following the ra mp-down cycle if enabled, will drive the output signals to the inactive state. pwmoutxx+ is dr iven low and pwmo utxx- is driven high. 7.3.6 power down (pdn) default = 1 0 - normal operation 1 - power down function: the entire device will enter a low-power state when this function is enabled, and t he contents of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation can occur. 7.4 pwm channel power down control (address 03h) 7.4.1 power down pwm channels (pdn_pwmb3:pdn_pwma1) default = 11111111 0 - normal operation 1 - power down pwm channel function: the specific pwm channel is in the power-down state. all processing is halted for the specific channel, but does not alter the setup or delay register values. the pwm output signals are driven to the appropriate logic level as defined by the po wer-down output mode bit, pdn_output_mode. when set to normal operation, the specific c hannel will power up according to the stat e of the ramp[1:0] bits and the channel output configuration selected. when transitioning from normal operation to power down, the specific chan- nel will power down according to the state of the ramp[1 :0] bits and the channel output configuration se- lected. ramp control is found in ?ramp configuration (address 05h)? on page 54 . 76543210 reserved reserved pdn_pwmb3 pdn_pwma3 pdn_pwmb2 pdn_pwma2 pdn_pwmb1 pdn_pwma1
ds633pp1 51 cs44600 7.5 misc. configuration (address 04h) 7.5.1 digital interface format (difx) default = 001 function: these bits select the digital interface format used for the dai serial port. the required relationship be- tween the left/right clock, serial clock, and serial da ta is defined by the digit al interface format and the options are detailed in figures 17 - 22. 7.5.2 am frequency h opping (am_freq_hop) default = 0 function: enables the modulator to alter the pwm switch timi ngs to remove interference when the desired frequen- cy from an am tuner is positioned near the pwm s witching rate. the pwm modulator circuitry must first be powered down using the pdn bit in the clock conf iguration and power control (address 02h) register before this feature can be enabled . there will be a delay fo llowing the power-up seq uence due to the re- locking of the src. once this feature is enabled, the output switch rate is divided by 2.25, resulting in a lowered pwm switch rate. care s hould be taken to ensure that: pwm_mclk / 16 > the upper frequency limit of the am tuner used 7.5.3 freeze controls (freeze) default = 0 function: this function will freeze the previous output of , and allow modifica tions to be made to the master volume control (address 07h-08h), channel xx volume contro l (address 09h-12h), and channel mute (address 13h) registers without the changes taking effect until the freeze bit is disabled. to make multiple chang- es in these control port registers take effect si multaneously, enable the freeze bit, make all register changes, then disable the freeze bit. 7654 3210 dif2 dif1 dif0 reserved am_freq_hop freeze dem1 dem0 dif2 dif1 dif0 description figure 0 0 0 left-justified, up to 24-bit data 18 0 0 1 i2s, up to 24-bit data 17 0 1 0 right-justified, 16-bit data 19 0 1 1 right-justified, 24-bit data 19 1 0 0 one-line mode #1, 20-bit data 20 1 0 1 one-line mode #2, 24-bit data 21 1 1 0 tdm mode, up to 32-bit data 22 table 5. digital audio interface formats
52 ds633pp1 cs44600 7.5.4 de-emphasis control (dem[1:0]) default = 00 00 - no de-emphasis 01 - 32 khz de-emphasis filter 10 - 44.1 khz de-emphasis filter 11 - 48 khz de-emphasis filter function: enables the appropriate digital filter to maintain the standard 15 ms/50 ms digital de-emphasis filter re- sponse. 7.6 ramp configuration (address 05h) 7.6.1 ramp-up/down setting (ramp[1:0]) default = 00 00 - ramp-up and ramp-down are disabled 01 - ramp-up is disabled. ramp-down is enabled. 10 - reserved 11 - ramp-up and ramp-down are enabled. note that after a ramp-up sequence has completed, audio will not play until ramp[1:0] is set to 01. function: when ramping is enabled, the duty cycle of the output pwm signal is increased (ramp-up) or decreased (ramp-down) at a rate determined by the ramp speed variable (ramp_spdx). this function is used in single-ended applications to reduce pops in the ou tput caused by the dc-blo cking capacitor. when the ramp-up/down function is disabled in single-ended applic ations, there will be an abrupt change in the out- put signal. refer to section 5.1.1 . if ramp-up or down is not needed, as in a full-bridge application, these bits shou ld be set to 00. if ramp- up or down is needed, as in a single-ended half-bridge application, these bits must be used in the proper sequence as outlined in ?recommended power-up sequence? on page 43 and ?recommended power- down sequence? on page 45 . 7.6.2 ramp speed (ramp_spd[1:0]) default = 01 00 - ramp speed = approximately 0.1 seconds 01 - ramp speed = approximately 0.2 seconds 10 - ramp speed = approximately 0.3 seconds 11 - ramp speed = approximately 0.65 seconds function: this feature is used in single-ended applications to reduce pops in the output caused by the dc-blocking capacitor. the ramp speed sets the time for the pw m signal to linearly ramp-up and down from the bias point (50% pwm duty cycle). refer to section 5.1.1 76543210 reserved reserved reserved ramp1 ramp0 reserved ramp_spd1 ramp_spd0
ds633pp1 53 cs44600 7.7 volume control conf iguration (address 06h) 7.7.1 single volume control (sngvol) default = 0 function: the individual channel volume levels are independently controlled by their respec tive volume control reg- isters when this function is disabled. when enable d, the volume on all channels is determined by the a1 channel volume control register. the other volume control registers are ignored. 7.7.2 soft ramp and zero cross control (szc[1:0]) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is select ed, all level changes will take effect immediately in one step. zero cross zero cross enable dict ates that signal level cha nges, either by attenuation changes or muting, will occur on a signal zero crossing to mini mize audible artifacts. the reques ted level change will occur after a tim- eout period (approximately 18.7 ms for a pwm switch rate of 384/768 khz and 17.0 ms for a pwm switch rate of 421.875/843.75 khz) if the signal does not enc ounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that si gnal level changes, either by attenuation changes or muting, will occur in 1/8-db steps and be implemented on a signal zero crossing. the 1/8-db level change will occur after a timeout period (approximately 18. 7 ms for a pwm switch rate of 384/768 khz and 17.0 ms for a pwm switch rate of 421.875/843.75 khz) if the signal d oes not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 7.7.3 enable 50% duty cycle fo r mute condition (mute_50/50) default = 0 0 - disabled 1 - enabled function: this bit enables the modulator to output an exact 50 %-duty-cycle pwm signal (not modulated), which cor- responds to digital silence, for all mute conditions. the muting function is affected, similar to volume con- 76543210 sngvol szc1 szc0 reserved mute_50/50 srd_err sru_err amute
54 ds633pp1 cs44600 trol changes, by the soft and zero cross bits (szc[1:0]). this bit does not cause a mute condition to occur. the mute_50/50 bit only defines oper ation during a normal mute condition. when mute_50/50 is set and a mute condition occurs, psr will not affe ct the output of the modulator, regardless if psr is enabled. output noise may be incr eased in this case if the noise on the high voltage power supply is greater than the system noise. theref ore, it is recommended that if a noisy power supply is used in a single-ended half-bridge configuratio n with psr enabled, mute_50/50 should be disabled and a normal, modulated mu te should be used. this will allow th e modulator to use the psr feedback to reject power supply noise and improve system performance. 7.7.4 soft ramp-down on interface error (srd_err) default = 0 0 - disabled 1 - enabled function: a mute will be performed upon detection of a timing error on the digital audio interface or if an src_lock error has occurred. an src_lock interrupt is an indication that the sample rate converter timings have become unstable, or have changed abrupt ly. audio data from the src is no longer consid- ered valid and could cause unwanted pops or clicks. when this feature is enabled, this mute is affected, similar to atte nuation changes, by the soft and zero cross bits (szc[1:0]). when disabled, an immediat e mute is performed on detection of an error. note: for best results, it is recomme nded that this bit be used in conjunction with the sru_err bit. 7.7.5 soft ramp-up on recover ed interface error (sru_err) default = 0 0 - disabled 1 - enabled function: an un-mute will be pe rformed after a mclk/l rck ratio change, recovered da i timing error, or after the src has gained lock. when this feature is enabled, this un-mute is affected, similar to attenuation chang- es, by the soft and zero cross bits (szc[1:0]). w hen disabled, an immediate un-mute is performed in these instances. note: for best results, it is recomme nded that this bit be used in conjunction with the srd_err bit. 7.7.6 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the pwm converters of t he cs44600 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-static data will releas e the mute. detection and muting is done independently for each channel. the muti ng function is affected, similar to volume control changes, by the soft and zero cross bits (szc[1:0]).
ds633pp1 55 cs44600 7.8 master volume control - integer (address 07h) 7.8.1 master volume control - integer (mstr_ivol[7:0]) default = 00000000 function: the master volume control - integer register allows gl obal control of the signal levels on all channels in 1 db increments from +24 to -127 db. volume settin gs are decoded as shown in table 6. the volume changes are implemented as specified by the soft an d zero cross bits (szc[1:0]). all volume settings greater than 00011000b are equivalent to +24 db. binary values for integer volume settings less than 0 db are in two?s complement form. 7.9 master volume contro l - fraction (address 08h) 7.9.1 master volume control - fraction (mstr_fvol[1:0]) default = 00 00 - +0.00 db 01 - +0.25 db 10 - +0.50 db 11 - +0.75 db function: the master volume control - fraction register is an additional offset to the value in the master volume control - integer register and allows global control of the signal levels on all channels in 0.25 db incre- ments. volume settings are decoded as shown in table 7. these volume changes are implemented as specified by the soft and zero cross bits (szc[1:0 ]). all volume settings greater than 00011000b are equivalent to +24 db. binary values for integer and fractional volume settings less than 0 db are in two?s complement form. to calculate from a positive decimal integer:fraction value to a binary positive integer:fraction value, do the following: 1. convert the decimal integer to binary. this is mstr_ivol[7:0]. 2. select the bit representation of the desired 0. 25 fractional increment. this is mstr_fvol[1:0]. to calculate from a negative decimal integer:fraction value to a binary, 2?s complement integer:fraction value, do the following: 76543210 mstr_ivol7 mstr_ivol6 mstr_ivol5 mstr_ivol4 mstr_ivol3 mstr_ivol2 mstr_ivol1 mstr_ivol0 mstr_ivol[7:0] hex value volume setting 0001 1000 18 +24 db 0001 0111 17 +23 db 0000 0001 01 +1 db 0000 0000 00 0 db 1111 1111 ff -1 db 1111 1110 fe -2 db 1000 0001 81 -127 db table 6. master inte ger volume settings 76543210 reserved reserved reserved reserved reserved reserved mstr_fvol1 mstr_fvol0
56 ds633pp1 cs44600 1. convert the decimal integer to binary. this is mstr_ivol[7:0]. 2. select the bit representation of the desired 0.25 fractional increment. this is mstr_fvol[1:0]. 3. concatenate mstr_ivol[7:0]: mstr_fvol[1:0] to form a 10-bit binary value. 4. perform a 2?s complement conversion on all 10 bits. the upper 8 bits are now the new mstr_fvol[7:0] and the two lower bits are mstr_fvol[1:0]. to convert from a 2?s complement integer:fracti on value to a negative decimal, do the following: 1. concatenate mstr_ivol[7:0]: mstr_fvol[1:0] to form a 10-bit binary value. 2. perform a 2?s complement conversion on all 10 bits. 3. convert the 10-bit binary number to a decimal value. 4. divide the decimal value by 4. mstr_ivol[7:0] mstr_fvol(1:0) volume setting 0001 1000 00 +24.00 db 0001 0111 10 +23.50 db 0000 0001 11 +1.75 db 0000 0001 00 +1.00 db 0000 0000 01 +0.25 db 0000 0000 00 0 db 1111 1111 10 -0.50 db 1111 1111 00 -1.00 db 1111 1110 11 -1.25 db 1111 1101 10 -2.50 db 1000 0010 00 -126.00 db 1000 0001 11 -126.25 db 1000 0001 00 -127.00 db table 7. master fractional volume settings
ds633pp1 57 cs44600 7.10 channel xx volume contro l - integer (addresses 09h - 0eh) 7.10.1 channel volume contro l - integer (chxx_ivol[7:0]) default = 00000000 function: the channel x volume control - integer register allows global contro l of the signal levels on all channels in 1 db increments from +24 to -1 27 db. volume settings are decoded as shown in table 6. the volume changes are implemented as specified by the soft an d zero cross bits (szc[1 :0]. all volume settings greater than 00011000b are equivalent to +24 db. binary values for integer volume settings less than 0 db are in two?s complement form. 7.11 channel xx volume contro l1 - fraction (address 11h) 7.12 channel xx volume cont rol2 - fraction (address 12h) 7.12.1 channel volume contro l - fraction (chxx_fvol[1:0]) default = 00 00 - +0.00 db 01 - +0.25 db 10 - +0.50 db 11 - +0.75 db function: the channel x volume control - fraction register is an additional offset to the value in the channel vol- ume control - integer register and allows global control of the signal levels on all channels in 0.25 db in- crements. volume settings are decoded as shown in table 7. these volume changes are implemented as specified by the soft and zero cross bits (szc[1 :0]). all volume settings greater than 00011000b are equivalent to +24 db. binary values for integer and fractional volume settings less than 0 db are in two?s complement form. see ?master volume control - fraction (address 08h)? on page 57 for hints on converting decimal num- bers to 2?s complement binary values. 76543210 chxx_ivol7 chxx_ivol6 chxx_ivol5 chxx_ivol4 chxx_ivol3 chxx_ivol2 chxx_ivol1 chxx_ivol0 chxx_ivol[7:0] hex value volume setting 0001 1000 18 +24 db 0001 0111 17 +23 db 0000 0001 01 +1 db 0000 0000 00 0 db 1111 1111 ff -1 db 1111 1110 fe -2 db 1000 0001 81 -127 db table 8. channel integer volume settings 76543210 chb2_fvol1 chb2_fvol0 cha2_fvol1 cha2_fvol0 chb1_fvol1 chb1_fvol0 cha1_fvol1 cha1_fvol0 76543210 reserved reserved reserved reserved chb3_fvol1 chb3_fvol0 cha3_fvol1 cha3_fvol0
58 ds633pp1 cs44600 7.13 channel mute (address 13h) 7.13.1 independent channel mute (chxx_mute) default = 0 0 - disabled 1 - enabled function: the pwm outputs of the cs44600 will mu te when enabled. the muting functi on is affected, similar to at- tenuation changes, by the soft and zero cross bits (szc[1:0]). 7.14 channel invert (address 14h) 7.14.1 invert signal polarity (chxx_inv) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the sign al polarity of their respective channels. chxx_ivol[7:0] chxx_fvol(1:0) volume setting 0001 1000 00 +24.00 db 0001 0111 10 +23.50 db 0000 0001 11 +1.75 db 0000 0001 00 +1.00 db 0000 0000 01 +0.25 db 0000 0000 00 0 db 1111 1111 10 -0.50 db 1111 1111 00 -1.00 db 1111 1110 11 -1.25 db 1111 1101 10 -2.50 db 1000 0010 00 -126.00 db 1000 0001 11 -126.25 db 1000 0001 00 -127.00 db table 9. channel fractional volume settings 76543210 reserved reserved chb3_mute cha3_mute chb2_mute cha2_mute chb1_mute cha1_mute 76543210 reserved reserved chb3_inv cha3_inv chb2_inv cha2_inv chb1_inv cha1_inv
ds633pp1 59 cs44600 7.15 peak limiter control register (address 15h) 7.15.1 peak signal limit all channels (limit_all) default = 0 0 - individual channel 1 - all channels function: when set to 0, the peak signal lim iter will limit the maximum signal amp litude to prevent clipping on the specific channel indicati ng clipping. the other channels will not be affected. when set to 1, the peak signal limiter will limit the maximum signal amplitude to prev ent clipping on all channels in response to any single channel indicating clipping. 7.15.2 peak signal limiter enable (limit_en) default = 0 0 - disabled 1 - enabled function: the cs44600 will limit the maximum si gnal amplitude to prevent clippi ng when this fu nction is enabled. peak signal limiting is performed by digital attenuat ion. the attack rate is determined by the limiter at- tack rate register. 7.16 limiter attack rate (address 16h) 7.16.1 attack rate (arate[7:0]) default = 00010000 function: the limiter attack rate is user se lectable. the effect ive rate is a function of the src output sampling fre- quency and the value in the limiter attack rate re gister. rates are calculated using the function rate = (32/{value})/src fs, where {value} is the decimal value in the limiter attack rate register and src fs is the output sample rate of the src which is determined by the pwm master clock frequency. src fs equals 384 khz for 24.576 mhz based cloc ks and 421.875 khz for 27.000 mhz based clocks. note: a value of zero in this register is not recommended , as it will induce erratic behavior of the limiter. use the lim_en bit to disable the limiter function (see peak limiter control register (address 15h) ). 76543210 reserved reserved reserved reserved reserved reserved limit_all limit_en 76543210 arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0
60 ds633pp1 cs44600 7.17 limiter release ra te (address 17h) 7.17.1 release rate (rrate[7:0]) default = 00100000 function: the limiter release rate is user sele ctable. the effective rate is a func tion of the src output sampling fre- quency and the value in the release rate regi ster. rates are calculated using the function rate = (512/{value})/src fs, where {value} is the decim al value in the release rate register and src fs is the output sample rate of the src which is determined by the pwm master clock frequency. src fs equals 384 khz for 24.576 mhz based clocks and 421.875 khz for 27 .000 mhz based clocks. note: a value of zero in this register is not recommend ed, as it will induce errati c behavior of the limiter. use the lim_en bit to disable the limiter function (see peak limiter control register (address 15h) ). 7.18 chnl xx load compensatio n filter - coarse adjust (addresses 18h, 1ah, 1ch, 1eh, 20h, 22h) 7.18.1 channel compensation filter - coarse adjust (chxx_cors[5:0]) default = 000000 function: the channel load compensation filter coarse adjust ment settings control the amount of attenuation of this single-pole filter and are used in conjunction wit h the fine adjustment bits to compensate for speaker impedance load variations. each pwm channel is co ntrolled by an associated register. the coarse ad- justment bits will attenuate the audio response curve according to the table below in 0.1 db increments. filter setting values less than -4.0 db will cause the pwm output to mute. binary code decimal value attack rate - 384 khz ( s per 1 / 8 db ) attack rate - 421.875 khz ( s per 1 / 8 db ) 00000001 1 83.33 75.852 00010100 20 4.167 3.793 00101000 40 2.083 1.896 00111100 60 1.389 1.264 01011010 90 0.926 0.843 table 10. limiter attack rate settings 76543210 rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 binary code decimal value release rate - 384 khz ( s per 1 / 8 db ) release rate - 421.875 khz ( s per 1 / 8 db ) 00000001 1 1333.333 1213.630 00010100 20 66.667 60.681 00101000 40 33.333 30.341 00111100 60 22.222 20.227 01011010 90 14.815 13.485 table 11. limiter re lease rate settings 76543210 reserved reserved chxx_cors5 chxx_cors4 chxx_ cors3 chxx_cors2 chxx_cors1 chxx_cors0
ds633pp1 61 cs44600 7.19 chnl xx load compensati on filter - fine adjust (addresses 19h, 1bh, 1dh, 1fh, 21h, 23h) 7.19.1 channel compensation filter - fine adjust (chxx_fine[5:0]) default = 000000 function: the channel load compensation filter fine adjustment settings control the amount of attenuation of this single-pole filter which follows th e coarse adjustment compensation filter. these bits are used in con- junction with the coarse adjustment bits to fine tune the total frequency respon se of the system to com- pensate for speaker impedance load variations. each pwm channel is controlled by an associated register. the fine adjustment bits will attenuate the audio response curv e according to the table below in 0.1 db increments. filter setting values less than -4.0 db will cause th e pwm output to mute. 7.20 interrupt mode control (address 28h) 7.20.1 interrupt pin control (int1/int0) default = 00 00 - active high, high output indi cates interrupt condition has occurred 01 - active low, low output indicates an interrupt condition has occurred 10 - open drain, active low. requires an external pull-up resistor on the int pin. 11 - reserved function: determines how the interrupt pin (int) will indicate an interrupt condit ion. if any of the mask bits in the interrupt mask register are set to a 1b, read the in terrupt status register to determine which condition caused the interrupt. chxx_cors[5:0] coarse filter setting 000000 0 db 000001 -0.1 db 001010 -1.0 db 011001 -2.5 db 100000 -3.2 db 101000 -4.0 db table 12. channel load compensation filter coarse adjust 76543210 reserved reserved chxx_fine5 chxx_fine4 chxx_fine3 chxx_fine2 chxx_fine1 chxx_fine0 chxx_fine[5:0] fine filter setting 000000 0 db 000001 -0.1 db 001010 -1.0 db 011001 -2.5 db 100000 -3.2 db 101000 -4.0 db table 13. channel load compensation filter fine adjust 76543210 int1 int0 reserved reserved reserved reserved reserved ovfl_l/e
62 ds633pp1 cs44600 7.20.2 overflow level/e dge select (ovfl_l/e) default = 0 function: this bit defines the ovfl interrupt type (0 = level sensit ive, 1 = edge trigger). the over flow status of all the audio channels when configured as ?e dge trigger? is cleared by reading the channel over flow status (address 2bh) (read only) , and by reset. after a reset this bit defa ults to 0b, specifyi ng ?level sensitive?. 7.21 interrupt mask (address 29h) default = 00000000 function: the bits of this register serve as a mask for the inte rrupt sources found in the interrupt status register. if a mask bit is set to 1b, the interrup t is unmasked, meaning that its occu rrence will affect the int pin and the interrupt status register. if a mask bit is set to 0b, the condition is masked, meaning that its occurrence will not affect the int pin. the bit positions align with the co rresponding bits in the interrupt status register. the mask bits for the gpio_int in terrupt are located in the gpio interrupt mask register. 7.22 interrupt status (address 2ah) (read only) for all bits in this register, a ?1? means the associat ed interrupt condition has occurred at least once since the register was last read. a ?0? me ans the associated interrupt condition has not occurred since the last reading of the register. reading the register resets the src_unlock, src_lock, rmpup_done, rmpdn_done and mute_done bits to 0. these bi ts are considered ?edge-trigger? interrupts. the ovfl_int and gpio_int bits will not reset to 0 by reading this re gister. the ovfl_int bit will be set to 0 by a read to the ?channel over flow status (address 2bh) (read only)? on page 66 only when the in- terrupt type is set to ?edge-t rigger?. the gpio_int bit will be set to 0 by a read to the ?gpio status register (address 2fh)? on page 67 only when the interrupt type is set to ?edge trigger?. if either of these interrupt types are configured as ?level sens itive?, then reading the appropriate status register will not clear the cor- responding status bit in this regist er. ovfl_int or gpio_int will remain se t as long as the logic active level is present. once the level is cleared, then a read to the proper status re gister will clear the status bit. 7.22.1 src unlock inte rrupt (src_unlock) default = 0 function: when high, indicates that the dai interface has detect ed an error condition and/or the src has lost lock. conditions which cause the src to loose lock, such as loss of dai_ lrck, dai_mclk or a dai_lrck/ dai_mclk ratio change, will cause an interrupt condit ion. this interrupt is an edge-triggered event. if this bit is set to a 1b, indicati ng an unlock condition, and an src_lock interrupt is detected, then this bit will be reset to 0b before a read of the interrupt status register. on ly the last valid state of the src will be reported. 765 4 3210 m_src_unlock m_src_lock m_rmpup_done m_rmpd n_done m_mute_done m_ovfl_int reserved reserved 7 6 5 4 3210 src_unlock src_lock rmpup_done rmpdn_do ne mute_done ovfl_int gpio_int reserved
ds633pp1 63 cs44600 7.22.2 src lock interrupt (src_lock) default = 0 function: when high, indicates that on all ac tive channels, the sample rate co nverters have achieved lock. this interrupt is an edge-triggered event. if this bit is set to a 1b, indicating a lock condition , and an src_unlock conditio n is detected, then this bit will be reset to 0b before a read of the interrupt status register. on ly the last valid state of the src will be reported. 7.22.3 ramp-up complete interrupt (rmpup_done) default = 0 function: when high, indicates that all active channels have completed the configured ramp-up interval. 7.22.4 ramp-down complete interrupt (rmpdn_done) default = 0 function: when high, indicates that all active channels have completed the configured ramp-down interval. 7.22.5 mute complete interrupt (mute_done) default = 0 function: when high, indicates that all muted channels have co mpleted the mute cycle-down interval as defined by the szc[1:0] bits in the ?volume control configuration (address 06h)? on page 55 . 7.22.6 channel over flow interrupt (ovfl_int) default = 0 function: when high, indicates that the magnitude of an output sample on one of the channels has exceeded full scale and has been clipped to positive or negative full scale as appropriate. this bit is the logical or of all the bits in the channel over flow status register. read the channel over fl ow status register to determine which channel(s) had the overflow condition. 7.22.7 gpio interrupt condi tion (gpio_int) default = 0 function: when high, indicates that a transition as configured on one of the un-masked gpio pins has occurred. this bit is the logical or of all the supported un-mask ed bits in the gpio status register. read the gpio status register to determine which gpio input(s) caused the interrupt condition. the gpio interrupt is not removed by reading this register. the gpio status register must be read to clear this interrupt. if the gpio input is configured as ?edge tr igger? the inte rrupt will clear. if the gpio in put is configured as ?level sensitive?, the interrupt condition will remain as long as the gpio in put remains at the active level.
64 ds633pp1 cs44600 7.23 channel over flow stat us (address 2bh) (read only) for all bits in this register, a ?1? means the associated condition has occurred at l east once since the register was last read. a ?0? means the associated condition has not occurred since the last reading of the register. reading the register resets all bits to 0 if the over flow level/edge interrupt type is set to ?edge trigger?. these channel overflow status bits are not effected by the interrupt mask bit, m_ovfl_int. the overflow condition of each channel can be polled instead of generating an interrupt as required. 7.23.1 chxx_ovfl default = 0 function: when high, indicates that the magnitude of the curr ent output sample on the associated channel has ex- ceeded full scale and has been clipped to positive or negative full scale as appropriate. 7.24 gpio pin in/out (address 2ch) 7.24.1 gpio in/out sel ection (gpiox_i/o) default = 0 0 - general purpose input 1 - general purpose output function: general purpose input - the pin is configured as an input. general purpose output - the pin is configured as a general purpose output. 7.25 gpio pin polari ty/type (address 2dh) 7.25.1 gpio polarity/type selection (gpiox_p/t) default = 1 function: general purpose input - if the pin is configured as an input, this bit defines the input polarity (0 = active low, 1 = active high). general purpose output - if the pin is configured as a genera l purpose output, this bit defines the gpio output type (0 = cmos, 1 = open-drain). 76543210 reserved reserved chb3_ovfl cha3_ovfl chb 2_ovfl cha2_ovfl chb1_ovfl cha1_ovfl 76543210 reserved gpio6_i/o gpio5_i/o gpio4_i/o gpio3_i/o gpio2_i/o gpio1_i/o gpio0_i/o 76543210 reserved gpio6_p/t gpio5_p/t gpio4_p/t gpio3_p/t gpio2_p/t gpio1_p/t gpio0_p/t
ds633pp1 65 cs44600 7.26 gpio pin level/edge trigger (address 2eh) 7.26.1 gpio level/edge input sensitive (gpiox_l/e) default = 0 function: general purpose inpu t - this bit defines the gpio input type (0 = level sensitive, 1 = edge trigger) when a gpio pin is configured as an input. the gpio pin st atus of an input configured as ?edge trigger? is cleared by reading the gpio status register when not enabled to ge nerate an interrup t (mask bit equals 0b) and by reset. after a reset this bit defaul ts to 0b, specifying ?level sensitive?. general purpose output - not used. 7.27 gpio status register (address 2fh) 7.27.1 gpio pin status (gpiox_status) default = x function: general purpose inpu t - bits in this register are read only when the corresponding gpio pin is configured as an input. each bit indicates the status of the gp io pin. the corresponding bit of a gpio input config- ured as ?edge trigger? is cleared by reading the gpio status register. gpio in puts configured as ?level sensitive? will not be automatically cl eared, but will reflect the logic stat e on the gpio input. the mask bits in the gpio interrupt ma sk register have no effect on the operation of these status bits. when a gpio is un-masked and enabled to generate an interrupt, and is configured as ?edge trigger?, a read operation to this register will cl ear the status bit and re move the interrupt condit ion. a read operation to the interrupt status (address 2ah) (read only) when a gpio is configured to generate an interrupt con- dition will not clear any bits in this register. general purpose output - for gpio pins configured as outputs, these bits are used to control the output signal level. a 1b written to a particular bit will c ause the correspondin g gpio pin to be driven to a logic high. a 0b will cause a logic low. 76543210 reserved gpio6_l/e gpio5_l/e gpio4_l/e gpio3_l/e gpio2_l/e gpio1_l/e gpio0_l/e 76 543210 reserved gpio6_status gpio5_status gpio4_status gpio 3_status gpio2_status gpio1_status gpio0_status
66 ds633pp1 cs44600 7.28 gpio interrupt mask register (address 30h) 7.28.1 gpio pin interr upt mask (m_gpiox) default = 0 function: general purpose inpu t - the bits of this register serve as a mask for gpio[3:0] interrupt sources. if a mask bit is set to 1, the interr upt is unmasked, meaning that its occurren ce will affect the int pin and the inter- rupt status register. if a mask bit is set to 0, the condition is masked, meanin g that its occurrence will not affect the int pin or interrupt stat us register. the proper pin status will be reported in the gpio status register. the bit positions align with the corres ponding bits in the gpio status register. general purpose output - this register is not used. 7.29 pwm configuration re gister (address 31h) 7.29.1 over sample rate selection (osrate) default = 0 0 - modulated pwm output pulses run at single-mode switch rate. typically 384 khz or 421.875 khz. 1 - modulated pwm output pulses run at double-mo de switch rate. typically 768 khz or 843.75 khz. function: enables the interpolation filter in the modulator to over-sample the incoming audio to support a double- speed pwm switch rate. this parame ter can only be changed when all modulators and associated logic are in the power-down state by setting the pdn bit in the register ?clock configuratio n and power control (address 02h)? on page 51 to a 1b. attempts to write this register while the pdn is not set will be ignored. 7.29.2 channels a1 and b1 output configuration (a1/b1_out_cnfg) default = 0 0 - pwm outputs for both channels a1 and b1 are configured for half-bridge operation 1 - pwm outputs for both channels a1 and b1 are configured for full-bridge operation function: identifies the output configuration. the value selected for this bit is applicable to the outputs for channels a1 and b1. this parameter can only be changed when all modulators and associated logic are in the pow- er-down state by setting th e pdn bit in the register ?clock configuration and po wer control (address 02h)? on page 51 to a 1b. attempts to write this register wh ile the pdn is not set will be ignored. 7.29.3 channels a2 and b2 output configuration (a2/b2_out_cnfg) default = 0 0 - pwm outputs for both channels a2 and b2 are configured for half-bridge operation 1 - pwm outputs for both channels a2 and b2 are configured for full-bridge operation function: identifies the output configuration. the value selected for this bit is applicable to the outputs for channels a2 and b2. this parameter can only be changed when all modulators and associated logic are in the pow- 76543210 reserved reserved reserved reserved m_gpio3 m_gpio2 m_gpio1 m_gpio0 76 5 4 3 2 1 0 osrate reserved reserved a1/b1_out_cnfg a2/ b2_out_cnfg a3_out_c nfg b3_out_cnfg reserved
ds633pp1 67 cs44600 er-down state by setting the pdn bit in the register ?clock configuration and power control (address 02h)? on page 51 to a 1b. attempts to write this regist er while the pdn is not set will be ignored. 7.29.4 channel a3 output configuration (a3_out_cnfg) default = 0 0 - pwm outputs for channel a3 are c onfigured for half-bridge operation 1 - pwm outputs for channel a3 are configured for full-bridge operation function: identifies the output confi guration. the value selected for this bit is applicable to the outputs for only chan- nel a3. this parameter can only be changed when all modulators and associated logic are in the power down state by setting the pdn bit in the register ?clock configuration and po wer control (a ddress 02h)? on page 51 to a ?1?b. attempts to wr ite this register while the pdn is not set will be ignored. 7.29.5 channel b3 output configuration (b3_out_cnfg) default = 0 0 - pwm outputs for channel b3 are c onfigured for half-bridge operation 1 - pwm outputs for channel b3 are configured for full-bridge operation function: identifies the output confi guration. the value selected for this bit is applicable to the outputs for only chan- nel b3. this parameter can only be changed when all modulators and associated logic are in the power- down state by setting the pdn bit in the register ?clock configuration and po wer control (a ddress 02h)? on page 51 to a 1b. attempts to write this regist er while the pdn is not set will be ignored. 7.30 pwm minimum pulse widt h register (address 32h) 7.30.1 disable pwmoutxx - signal (disable_pwmoutxx-) default = 0 0 - pwm minus (?-?) differential si gnal is operational when pwm channel is configured for half-bridge. 1 - pwm minus (?-?) differential si gnal is disabled when pwm channe l is configured for half-bridge. function: determines if the pwm minus (?-?) di fferential signal is disabled when the particular pwm channel is con- figured for half-bridge operation. this bit is ignored for channels configured for full-bridge operation. the value selected for this bit is app licable to the outputs for all channels configured for half-bridge operation. this parameter can only be changed when all modulators and associated logic are in the power-down state by setting the pdn bit in the register ?clock configuration and power control (address 02h)? on page 51 to a 1b. attempts to write this regist er while the pdn is not set will be ignored. 7.30.2 minimum pwm output puls e settings (min_pulse[4:0]) default = 00000 function: the pwm minimum pulse registers allow settings for t he minimum allowable pulse width on each of the pwmout differential signal pairs, pwmoutxx+ and pw moutxx-. the value select ed in this register is applicable to all pwm channels. the effective minimum pulse is calculated by multiplying the register val- ue by the period of the pwm_mclk. this parameter can only be changed when all modulators and as- sociated logic are in the power-down state by setting the pdn bit in the register ?clock configuration and 76543210 disable_pwmoutxx- reserved reserved min_pulse4 mi n_pulse3 min_pulse2 min_pulse1 min_pulse0
68 ds633pp1 cs44600 power control (address 02h)? on page 51 to a 1b. attempts to write this register while the pdn is not set will be ignored. 7.31 pwmout delay regi ster (address 33h) 7.31.1 differential signal delay (diff_dly[2:0]) default = 000 function: the differential signal delay bits allow delay adjus tment between each channel?s differential signals, pwmoutxx+ and pwmoutxx-. this set of bits control the delay between pwmoutxx+ and pw- moutxx- across all active channels. the value of this register determines the amount of delay inserted in the output path. the effective delay is calculated by multiplying the register value by the period of the pwm_mclk. this parameter can only be changed when all modulators and associated logic are in the power-down state by setting the pdn bit in the register ?clock configuration and power control (address 02h)? on page 51 to a 1b. attempts to writ e this register while the p dn is not set will be ignored. 7.31.2 channel delay sett ings (chnl_dly[4:0]) default = 00000 function: the channel delay bits allow delay adjustment of each of the pwmout differential signal pairs, pw- moutax+/pwmoutax- from the asso ciated pwmoutbx+/pwmout bx-. the value of this register de- termines the amount of delay inserted in the output pa th. the effective delay is calculated by multiplying the register value by the period of the pwm_mclk. this parameter can only be changed when all mod- ulators and associated logic are in the power-down state by setting the pdn bit in the register ?clock con- figuration and power control (address 02h)? on page 51 to a 1b. attempts to write this register while the pdn is not set will be ignored. binary code min_pulse[4:0] minimum pulse setting (multiply by pwm_mclk period) 00000 0 - no minimum 00110 6 10100 20 11111 31 table 14. pwm minimum pulse width settings 76543210 diff_dly2 diff_dly1 diff_dly0 chnl_dly4 chnl_dly3 chnl_dly2 chnl_dly1 chnl_dly0 binary code delay setting (multiply by pwm_mclk period) 000 0 - no delay 001 1 100 4 111 7 table 15. differential signal delay settings binary code delay setting(multiply by pwm_mclk period) 00000 0 - no delay 00110 6 11000 24 11111 31 table 16. channel delay settings
ds633pp1 69 cs44600 7.32 psr and power supply c onfiguration (address 34h) 7.32.1 power supply rejection enable (psr_en) default = 0 0 - disable 1 - enable function: enables the on-card and internal po wer supply rejection circuitry. this bit will cause the psr_en output signal to change logic leve l. a ?0?b in this bit will cause the psr_en to drive a logic low. a ?1?b will drive a logic high. 76 5 4 3 2 1 0 psr_en psr_reset feedback_en reserved reserved ps_sync_div2 ps_sync_div1 ps_sync_div0 pwmouta2+ pwmouta2- pwmoutb2+ pwmoutb2- tch dly tdif dly tdif dly pwmouta1+ pwmouta1- pwmoutb1+ pwmoutb1- tch dly tdif dly tdif dly pwmouta3+ pwmouta3- pwmoutb3+ pwmoutb3- tch dly tdif dly tdif dly figure 31. pwm output delay
70 ds633pp1 cs44600 7.32.2 power supply reject ion reset (psr_reset) default = 0 0 - force reset condition 1 - remove reset condition function: this bit is used to assert a reset condition to the on-card psr components. when set to a ?0?b, the psr_reset signal will be asserted low. the reset condition will continue as long as this bit is set to a ?0?b. this bit must be set to a ?1?b for proper psr operation. 7.32.3 power supply rejection feedback enable (feedback_en) default = 0 0 - disable 1 - enable function: enables the internal power supply rejection feedback logic. 7.32.4 power supply sync clock divi der settings (ps_sync_div[2:0]) default = 000 function: these three bits determine the divider for the xtal clock signal for generating the ps_sync clock signal. 7.33 decimator shift/scale (addresses 35h, 36h, 37h) 7.33.1 decimator shift (dec_shift[2:0]) default = 010 function: these bits are used to scale the power supply reading ( decimator outd (addresses 3bh, 3ch, 3dh) ) dur- ing the psr feedback calibration sequence. t he combination of shift and scale factors (dec_scale[18:0]*2^(dec_shift[2:0])) can be viewed as a floating point coefficient. the floating point coefficient will be determined during the psr feedback calibration sequence. see decimator scale (dec_scale[18:0]) register description and ?recommended psr calibration sequence? on page 44 . ps_sync_div[2:0] ps_sync clock divider 000 output disabled 001 divide by 32 010 divide by 64 011 divide by 128 100 divide by 256 101 divide by 512 110 divide by 1024 table 17. power supply sync clock divider settings 76543210 reserved dec_shift2 dec_shift1 dec_shift0 reserved dec_scale1 8 dec_scale17 dec_scale16 76543210 dec_scale15 dec_scale14 dec_scale13 dec_scale12 dec_scale11 dec_scale10 dec_scale09 dec_scale08 76543210 dec_scale07 dec_scale06 dec_scale05 dec_scale04 dec_scale03 dec_scale02 dec_scale01 dec_scale00
ds633pp1 71 cs44600 7.33.2 decimator scale (dec_scale[18:0]) default = 25868h function: these bits are used to scale the power supply reading ( decimator outd (addresses 3bh, 3ch, 3dh) ) dur- ing the psr feedback calibration sequence. dec_scale[ 18:0] has 19-bit precision, formatted as signed 1.18 with decimal values from -1 to 1-2^(-18). the combination of shift and scale factors (dec_scale[18:0]*2^(dec_shi ft[2:0])) can be viewed as a floating point coefficient. the floating point coefficient will be determined during t he psr feedback calibra tion sequence. see decimator shift (dec_shift[2:0]) register description and ?recommended psr calibration sequence? on page 44 . 7.34 decimator outd (addresses 3bh, 3ch, 3dh) 7.34.1 decimator outd (dec_outd[23:0]) default = 000000h (read only) function: these bits reflect the real-time power supply value as measured by the exte rnal psr feedback circuit. dec_outd[23:0] has 24-bit precision, formatted as si gned 2.22 with decimal values from -4 to 4-2^(-22). calibration needs to be done to correlate the valu e of dec_outd[23:0] with the real power supply value. a quiet dc power supply wit hout any ripple is treated as 1.0 with dec_outd[23:0] calibrated at 400000h. see ?recommended psr calibration sequence? on page 44 . dec_scale[18:0] dec_shift[2:0] calculated coefficient (c psr ) 20000h=0.5 001b=1 0.5*2^(1)=1 28851h=0.6331 010b=2 0.6331*2^(2)=2.5325 table 18. decimator shift/scale coefficient calculation examples 76543210 dec_outd23 dec_outd22 dec_outd21 dec_outd20 dec_outd19 dec_outd18 dec_outd17 dec_outd16 76543210 dec_outd15 dec_outd14 dec_outd13 dec_outd12 dec_outd11 dec_outd10 dec_outd09 dec_outd08 76543210 dec_outd07 dec_outd06 dec_outd05 dec_outd04 dec_outd03 dec_outd02 dec_outd01 dec_outd00
72 ds633pp1 cs44600 8. parameter definitions dynamic range (dr) the ratio of the rms value of the signal to the rms sum of all other spectral comp onents over the specified bandwidth, typically 20 hz to 20 khz. dynamic range is a signal-to-no ise ratio measurement over the spec- ified band width made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full-scale , with units in db fs a. this techniq ue ensures that the distortion components are below the noise level and do not effect the m easurement. this measurement technique has been ac- cepted by the audio engineering so ciety, aes17-1991, and the electronic industries asso ciation of japan, eiaj cp-307. frequency response (fr) fr is the deviation in signal level verses frequency. the 0 db reference point is 1 khz. the amplitude cor- ner, ac, lists the maximum deviatio n in amplitude above and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maxi- mum frequency inclusive. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each c hannel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv. db fs a db fs is defined as db relative to full-scale. the ?a? indicates an a weighting filter was used. differential nonlinearity the worst case deviation from the ideal code width. units in lsb. fft fast fourier transform. fs sampling frequency. resolution the number of bits in the ou tput words to the dacs, and in the input words to the adcs.
ds633pp1 73 cs44600 signal to noise ratio (snr) snr, similar to dr, is the ratio of an arbitrary sinuso idal input signal to the rms sum of the noise floor, in the presence of a signal. it is measured over a 20 hz to 20 khz bandwidth with units in db. src sample rate converter. converts data derived at one sample rate to a differing sample rate. the cs44600 operates at a fixed sample frequency. the internal samp le rate converter is used to convert digital audio streams playing back at other fr equencies to the pwm output rate. total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a.
74 ds633pp1 cs44600 9. references 1. cirrus logic, ? audio quality measurement specification ,? version 1.0, 1997. http://www.cirrus.com/pro ducts/papers/meas/meas.html 2. cirrus logic, ? an18: layout and design rules for data converters and other mixed signal devices ,? version 6.0, february 1998. 3. cirrus logic, ? an22: overview of digital audio interface data structures , version 2.0 ?, february 1998.; a useful tutorial on digita l audio specifications. 4. philips semiconductor, ? the i2c-bus specification: version 2 ,? dec. 1998. http://www.semiconductors.philips.com
ds633pp1 75 cs44600 10.package dimensions inches millimeters dim min nom max min nom max a --- 0.55 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.008 0.011 0.17 0.20 0.27 d 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 d1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 e1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e* 0.016 0.020 bsc 0.024 0.40 0.50 bsc 0.60 l 0.018 0.024 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mmcontrolling dimension is mm. jedec designation: ms022 figure 32. 64-pin lqfp package drawing note: see legend below 64l lqfp package drawing e1 e d1 d 1 e l b a1 a
76 ds633pp1 cs44600 11.thermal characteristics parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja - - 48 38 - - c/watt
ds633pp1 77 cs44600 12.revision history release date changes a1 may 2004 1st advance release a2 september 2004 updated lead-free device ordering information a3 october 2004 -updated ?features? on page 1 -updated ?external crystal operating frequency? on page 11 -updated ?typical full-bridge connection diagram? on page 22 -updated ?typical half-bridge connection diagram? on page 23 -updated section 4.2 "feature set summary" on page 22 -updated ?fsout domain clocking? on page 24 -updated ?sample rate converter? on page 31 -updated ?pwm engines? on page 32 -updated table 4, ?typical pwm switch rate settings,? on page 33 -updated section 4.5.8 "modulator" on page 33 -updated section 4.5.10 on page 34 -updated section 4.6.1 "spi mode" on page 35 -updated section 4.6.2 "i2c mode" on page 36 -updated section 5. "power supply, grounding, and pcb layout" on page 38 -updated section 5.1 "reset and power-up" on page 41 -updated section 5.1.1 "pwm popguard? transient control" on page 41 -updated section 5.1.2 "recommended power-up sequence" on page 41 -updated section 5.1.3 "recommended psr calibration sequence" on page 42 -updated section 5.1.4 "recommended power-down sequence" on page 43 -updated section 6. "register quick reference" on page 44 -updated section 7.5.2 "am frequency hopping (am_freq_hop)" on page 51 -updated section 7.6 "ramp configuration (address 05h)" on page 52 -updated section 7.7.3 on page 53 -corrected table 7, ?master fractional volume settings,? on page 56 -corrected table 9, ?channel fractional volume settings,? on page 58 -corrected table 11, ?limiter release rate settings,? on page 60 -updated table 7.18, ?chnl xx load compensation filter - coarse adjust (addresses 18h, 1ah, 1ch, 1eh, 20h, 22h),? on page 60 -updated table 7.19, ?chnl xx load compensation filter - fine adjust (addresses 19h, 1bh, 1dh, 1fh, 21h, 23h),? on page 61 -updated section 7.26 "gpio pin level/edge trigger (address 2eh)" on page 65 -updated section 7.29 "pwm configuration register (address 31h)" on page 66 pp1 may 2005 -updated ?features? on page 1 -updated ?ordering information? on page 2 -correcte ?power supply current? on page 9 -corrected ?high-level input voltage? on page 9 -corrected ?low-level input voltage? on page 9 -corrected ?high-level output voltage at io = -2 ma? on page 9 -corrected ?low-level output voltage at io = 2 ma? on page 9 -corrected ?digital filter response (note 12)? on page 11 -updated ?typical full-bridge connection diagram? on page 22 -updated ?typical half-bridge connection diagram? on page 23 -corrected figure 13 on page 23 -updated section 7.5.2 "am frequency hopp ing (am_freq_hop)" on page 51 table 19. revision history
78 ds633pp1 cs44600 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the informat ion is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version o f relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no responsibility is assu med by cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or ot her rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, m ask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herei n and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of c irrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. certain applications using semic onductor products may involve potential risks of death, personal in jury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into th e body, automotive safe ty or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer?s risk and cirrus discla ims and makes no warranty, express, statutory or implied, including the implied warra nties of merchantability and fitn ess for particular purpose, with regard to any cirrus product that is used in such a manner. if the cus tomer or customer?s customer uses or perm its the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs and popguard are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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